An overview on the physics and circuit design oriented background of the advanced compact model HICUM is presented. Related topics such as the approach employed for geometry scaling and parameter extraction are briefly discussed. A model hierarchy is introduced, that addresses a variety of requirements encountered during the increasingly complicated task of designing analog and high-frequency circuits.

This paper describes a system architecture along with signal processing technique which allows a reduction in the complexity of a 3.1-10.6 GHz Ultra-Wideband radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end down-converts the signal frequency by subsampling, thus, requiring substantially less hardware than a traditional narrowband approach. However, the simplified receiver front end shows a high sensitivity to timing offset. By proposing an analytic signal processing technique, the vulnerability of timing offset is mitigated; furthermore, a time resolution finer than the sampling period is achieved, which is useful for locationing or ranging applications. Analysis and simulations of system specifications are also provided in this paper.

An asymmetric Dual Metal Stack Gate (DMSG) SOI MOSFET transistor has been investigated for its enhanced electrical characteristics. A 2-D physical model has been proposed and its results have been confirmed by those obtained by simulation. These results predict better short channel effects such as drain induced barrier lowering (DIBL) characteristics and hot carrier effects for this device compared to those for conventional SOI MOSFETs. The effects of the Stacked Gate (SG) and Dual Metal Gate (DMG) structures on short channel effects are compared. It has been observed that SG reduces DIBL significantly, while DMG prevents the normal roll-off of the threshold voltage reduction.

A method to monitor the GaInP/GaAs HBT device structure including emitter ledge thickness is demonstrated in this paper. The base thickness and base doping density are obtained through base transit time and base sheet resistance measurements while the base transit time is measured through the cut-off frequency measurements at various bias points. A large size two-emitter HBT device is used to measure the ledge thickness. Emitter doping profile and collector doping profile are obtained by the large size HBT device through C-V measurements. An FATFET device formed by two emitters as drain and source terminals and the interconnect metal as the on-ledge Schottky gate between two emitters is used to measure the ledge thickness.

Direct parameter extraction is believed to be the most accurate method for equivalent-circuits modeling of heterojunction bipolar transistors (HBT's). Using this method, the parasitic elements, followed by the intrinsic elements, are determined analytically. Therefore, the quality of the extrinsic elements extraction plays an important role in the accuracy and robustness of the entire extraction algorithm. This study proposes a novel extraction method for the extrinsic elements, which have been proven to be strongly correlated with the intrinsic elements. By utilizing the specific correlation, the equivalent circuit modeling is reduced to an optimization problem of determining six specific extrinsic elements. Converting the intrinsic equivalent circuit into its common-collector configuration, all intrinsic circuit elements are extracted using exact closed-form equations for both the hybrid-π and the T-topology equivalent circuits. Additionally, a general explicit equation on the total extrinsic elements is derived, subsequently reducing the number of optimization variables. The modeling results are presented, showing that the proposed method can yield a good fit between the measured and calculated S parameters.

An ultralow power constant reference current circuit with low temperature dependence for micropower electronic applications is proposed in this paper. This circuit consists of a constant-current subcircuit and a bias-voltage subcircuits, and it compensates for the temperature characteristics of mobility µ, thermal voltage V_T, and threshold voltage V_TH in such a way that the reference current has small temperature dependence. A SPICE simulation demonstrated that reference current and total power dissipation is 97.7 nA, 1.1 µW, respectively, and the variation in the reference current can be kept very small within 4% in a temperature range from -20 to 100.

A structure of a track-and-hold (T/H) circuit based on a pair of complementary floating-gate (FG) MOS transistors is introduced. Its main features include low complexity, low operating supply voltage and gain insensitivity to device mismatches, leading to efficient realization of numerous baseband functions in modern communication systems. The detailed operation and performance analysis of the FG T/H circuit are given. Functional verification of the circuit is provided through a breadboard experiment. The effectiveness of the circuit is verified via simulations where the single T/H cell operating at 10 MHz clock frequency exhibits gain variation less than 0.13% and a dynamic range over 71 dB with the coupling capacitance of 300 fF at 1.5 V supply and 12.75 µW power consumption. As a demonstration on its practical viability, the designed FG T/H cell was also utilized to realize a 10 MS/s 7-tap analog correlator for possible use in modern communication applications.

High-Speed High-Resolution Comparators are integral parts of very high-speed high-resolution Analog-to-Digital Converters (ADC). Parallel successive-approximation and flash ADCS can boost conversion rates while providing high resolution, provided that accurate and fast offset-cancelled comparators could be implemented. Moreover, accurate offset cancellation is needed in accurate gain stages of other types of high speed ADCs as well. This has never been easy and creates a bottle neck for high-speed high-resolution ADCs. The reason is that conventional offset cancellation methods, suffer either from inaccurate cancellation or from slow operation. Hence, either speed or accuracy is compromised. This is due to the trade off of gain (accuracy) for bandwidth (speed) in conventional methods. Here, we introduce a new offset cancellation method which satisfies the need for both high-speed and accurate offset cancellation simultaneously.

This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hybrid cascode compensation are about 40 percent greater than those of the conventional cascode compensation. Circuit level simulation results are provided to show the accuracy of the calculated expressions and also the usefulness of the proposed cascode compensation technique.

A high-speed transconductance-C-opamp integrator using a current-feedback amplifier is proposed. The integrator has good frequency response compared with a conventional transconductance-C-opamp integrator using a voltage-feedback amplifier. The current-feedback amplifier shifts the second pole of the proposed integrator to the upper frequency. The frequency is proportional to the current gain of the current-feedback amplifier. The proposed integrator can eliminate effects of the parasitics at the output node of the transconductance since the voltage at the node is fixed. One of the circuit examples of the proposed integrator is shown. Its validity is confirmed through HSPICE simulations. The proposed integrator works as predicted up to 260 MHz.

In this paper, we propose a circuit configuration for the low-frequency second-order active RC BPF (band pass filter) which has stable high Q. This proposed circuit is a high Q low-frequency one with a small capacitance, which is realized by applying an output capacitance multiplier to the circuit. Then a detailed circuit analysis is performed for the proposed circuit. From the simulation results of f_o and Q for various combinations of circuit element values, we can confirm that the circuit realization of a center frequency of several Hz is possible by employing chip condensers of dozens of nF. The bread-board circuit of this configuration is confirmed to have small temperature dependences of f_o and Q by the experiment. It is also clarified from detailed noise analysis and noise measurement that the circuit noise is sufficiently maintained at a low level.

This paper proposes a genetic programming method to synthesize passive filter circuits. This method allows both the circuit topology and the component values to be evolved simultaneously. Experiments show that this method is fast and capable of generating circuits which are more economical than those generated by traditional design approaches. In addition, we take into account practical design considerations at high-frequency applications, where the component values are frequency-dependent and restricted to some discrete values. Experimental results show that our method can effectively generate not only compliant but also economical circuits for practical design tasks.

A method is proposed to compute moments of distributed coupled RLC interconnects. Both uniform line models and non-uniform line models will be developed. Considering both self inductances and mutual inductances in multi-conductors, recursive moment computations formulae of lumped coupled RLC interconnects are extended to those of distributed coupled RLC interconnects. By using the moment computation technique in conjunction with the projection-based order reduction method, the inductive crosstalk noise waveform can be accurately and efficiently estimated. Fundamental developments of the proposed approach will be described. Simulation results demonstrate the improved accuracy of the proposed method over the traditional lumped methods.

A feedforward-based active shielding technique for digital noise suppression is more preferred for its capability of reducing the noise on the entire area inside the guard ring. In order to compensate for the variation of substrate parameters, an automatic control scheme to tune the gain of the active shield circuit is proposed. Simulation results show the effectiveness of the proposed system in reducing the digital noise regardless of circuit layout. Simulation results also show that noise suppression improvement from passive guard ring to active shield with tuning is 20 dB or one tenth while that from active shield without tuning to active shield with tuning is 12 dB.

An even-harmonic mixer using a bipolar differential pair (bipolar harmonic mixer;BHMIX) is theoretically analyzed from the direct conversion point of view; i.e, conversion gain, third-order input intercept point (IIP3), self-mixing induced dc offset level, and second-order input intercept point (IIP2). Also, noise are analyzed based on nonlinear large-signal model, and numerical results are given. Noises are treated as cyclostationary noises, thus all the folding effects are taken into account. Factors determining IIP3, IIP2, dc offset, and noise are identified and estimation procedures for these characteristics are obtained. For example, design guidelines for the optimal noise performance are given. Measured results support all the analysis results, and they are very useful in the practical BHMIX design.

A DC offset caused by self-mixing is a serious problem for direct-conversion receivers. Local oscillation (LO) leakage via quadrature demodulators (QDEMOD) must be suppressed in order to achieve a low DC offset. An LO buffer which drives QDEMOD mainly causes the LO leakage. We proposed an LO buffer which has a high-pass frequency response with small occupied area and low current consumption. A QDEMOD using the proposed LO buffer is fabricated using a SiGe BiCMOS process. Measured low LO leakage of -70 dBm is achieved, which is 10 dB lower than that of a QDEMOD with a conventional LO buffer. This measured result indicates that the proposed LO buffer is suitable for QDEMODs for direct-conversion receivers.

A dual-mode, triple-band RF front-end receiver for GSM900, DCS1800 and WCDMA is presented in this paper. This chip uses low-IF and zero-IF receiver architectures for GSM and WCDMA respectively to fulfill the entirely different system requirements of the two standards. It consists of three parallel LNAs and down-conversion mixers with on-chip LO I/Q generations. The receiver front-end is implemented in a standard 0.25 µm CMOS process and consumes about 30-mA from a 2.7-V power supply for all modes. The measured double-side band noise figure and voltage gain are 3 dB, 36 dB for the GSM900, 5.9 dB, 31 dB for the DCS1800, and 4.3 dB, 29.6 dB for the WCDMA, respectively.

A 3-bit flash analog-to-digital converter (ADC) for electronic dispersion compensation (EDC) was developed using InP HBTs. Nyquist operation was confirmed up to 24 Gsps, which enables oversampling acquisition for 10 Gbit/s non-return-to-zero (NRZ) signals. The ADC can also be operated at up to 37 Gsps for low input frequencies. To reduce aperture jitter and achieve a wide band of over 7 GHz, an analog input signal for all pre-amplifiers and a clock signal for all latched comparators are provided as traveling waves through coplanar transmission lines. EDC was demonstrated by capturing a 10-Gbit/s pseudo-random bit stream (PRBS) with the waveform degraded by polarization-mode dispersion (PMD). By using the captured data, we confirmed that a calculation of a transversal filter mitigates PMD.

Intelligent robot control systems based on multiprocessors, sensors, and actuators require a flexible network for communicating various types of real-time data (e.g. sensing data, interrupt signals). Furthermore, serial data transfer implemented using a few wiring lines is also required. Therefore, a CDMA serial communication interface with a new two-step synchronization technique is proposed to counter these problems. The transmitter and receiver fabricated by 0.25 µm digital CMOS technology achieve 2.7 Gcps (gigachips per second) and can multiplex 7 communication channels.

This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 µm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.

A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm² including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.

A new approach is proposed in this paper for the tracking of the optimal operating frequency in a Class E backlight inverter using the phase-locked loop (PLL) technique. First, a new single-stage backlight module is introduced to simplify the circuit and to raise the system efficiency. A piezoelectric transformer (PT) is used to drive the cold cathode fluorescent lamp (CCFL) to eliminate the downside of a conventional transformer and to reduce the dimension of the backlight module. Next, a PLL is embedded in the backlight system, as a feedback mechanism, to track the optimal operating frequency of the PT so that the PT's temperature effect is removed and, hence, the system efficiency and stability is improved. The feedback variable proposed is a phase angle rather than a lamp current amplitude traditionally used. A simplified model, along with its design procedure, is next presented. The complete analysis and design considerations are detailed. Finally, it is rather encouraging to observe that the experimental results match our analytical solutions closely.

In a direct conversion receiver for mobile communication, it is important to reduce power dissipation. Because a low pass filter in a direct conversion receiver must suppress adjacent channel signals, a high order and high power dissipation is often required in the low pass filter. We propose a new phase compensation technique suitable for a low power transconductor used in a G_mC filter as a low pass filter. The new phase compensation technique reduces 10% of power dissipation.

This paper demonstrates a small compact 5.7 GHz upconversion Gilbert micromixer using 0.35 µm SiGe HBT technology. A micromixer has a broadband matched single-ended input port. A passive LC current combiner is used to convert micromixer differential output into a single-ended output and doubles the output current for single-ended-input and single-ended-output applications. Thus, a truly balanced operation of a Gilbert upconversion mixer with a single-ended input and a single-ended output is achieved in this paper. The fully matched upconversion micromixer has conversion gain of -4 dB, OP_{1 dB} of -9 dBm and OIP₃ of 4 dBm when input IF=0.3 GHz, LO=5.4 GHz and output RF=5.7 GHz. The IF input return loss is better than 18 dB for frequencies up to 20 GHz while RF output return loss is 25 dB at 5.7 GHz. The supply voltage is 3.3 V and the current consumption is 4.6 mA. The die size is 0.90.9 mm² with 3 integrated on-chip inductors.

A direct conversion receiver for W-CDMA, which consumes extremely low power, is presented. The receiver consists of a low-noise amplifier (LNA) IC, a receiver IC and other passive components such as an RF-SAW (Surface Acoustic Wave) filter. The receiver IC includes a quadrature demodulator (QDEM) with a local oscillator (LO) divider, low-pass filters (LPFs) for channel selection, variable gain amplifiers (VGAs) with dynamic range of 80 dB, and a fractional-N synthesizer. The power consumption for the entire receiver chain was only 30.8 mA at supply voltage of 2.7 V.

A RF front-end chip for a dual-band Global Positioning System (GPS) receiver for L1 and L2 bands is designed using 0.25 µm CMOS technology. All function blocks of the GPS front-end are integrated onto one chip. The low noise amplifier has input matching over a wide frequency range to handle the L1 and L2 bands. This receiver uses a dual-band image-reject mixer with the quadrature mixer sharing a transconductor stage. This configuration enables the RF blocks to be shared with the L1 and L2 bands. The receiver has a chip area of 3.16 mm3.16 mm, and consumes 35 mA at 2.5 V.

This paper presents a dual-band mixer equipped with a dual-band load using current combine technique to minimize chip area by sharing inductors for each frequency band. A systematic design methodology for the current combine load based on parasitic effect considerations is also developed. By following the proposed design procedure, the load inductance and combine capacitance for the dual-band mixer can be easily determined. A 2.4/5.2-GHz CMOS mixer design has been implemented to demonstrate the feasibility of the design technique.

This paper describes a method of extending the signal frequency bandwidth while increasing the stability of a CMOS transimpedance amplifier (TIA). The TIA consists of three inverting amplifiers in a series, and a high-pass filter plus a non-inverting amplifier that are connected to the last two inverting amplifiers stated above in parallel. The TIA is fabricated using a 0.35 µm CMOS process and realizes stable conversion of 60-dBΩ from the photodiode current to the output voltage with more than 500 MHz of signal frequency bandwidth and 60 mW of power consumption from a 3.3 V supply voltage.

A Spread Spectrum Clock Generator (SSCG) using Digital Tracking scheme (DT-SSCG) is described. Using digital tracking control outside a PLL, DT-SSCG can realize stable modulation characteristic independent of the PLL constants. Moreover, DT-SSCG can apply to various modulation profiles easily by brief change of the digital tracking parameters. A test chip has realized the fitting of 5000 ppm downspread with 6.02 dB and 8.02 dB spectrum peak reduction for triangle and Non-Linear modulation.

This paper presents a technique for reducing spurious output of balanced modulators used in transmitters and arbitrary waveform generators. Two-step upconversion is a convenient way to produce a desired single-sideband (SSB) radio-frequency (RF) signal--baseband quadrature I and Q signals (which are analog outputs of direct digital frequency synthesizers) are upconverted by mixers and local oscillators (LOs)--but mismatches between the DACs in I and Q paths cause spurious output. We propose a method of dynamically matching the I and Q paths by multiplexing two DACs between I and Q paths in a pseudo-random manner. MATLAB simulation shows that multiplexing the two DACs spreads the spurious output, caused by mismatches between the two DACs, in the frequency domain, and reduces the peak level of spurious signals.

In many electromagnetic field problems, matrix equations were always deduced from using the method of moment. Among these matrix equations, some of them might require a large amount of computer memory storage which made them unrealistic to be solved on a personal computer. Virtually, these matrices might be too large to be solved efficiently. A fast algorithm based on a Toeplitz matrix solution was developed for solving a bordered Toeplitz matrix equation arising in electromagnetic problems applications. The developed matrix solution method can be applied to solve some electromagnetic problems having very large-scale matrices, which are deduced from the moment method procedure. In this paper, a study of a computationally efficient order-recursive algorithm for solving the linear electromagnetic problems [Z]I = V, where [Z] is a Toeplitz matrix, was presented. Upon the described Toeplitz matrix algorithm, this paper derives an efficient recursive algorithm for solving a bordered Toeplitz matrix with the matrix's major portion in the form of a Toeplitz matrix. This algorithm has remarkable advantages in reducing both the number of arithmetic operations and memory storage.

A lasing charactrization of a Brillouin/erbium optical fiber laser (BEFL) is experimentally discussed. In the BEFL, an erbium-doped fiber amplifier (EDFA) is incorporated into the Brillouin laser resonator to enhance small Brillouin gain, which makes the configuration of the Brillouin laser resonator easy and flexible. The experimental results show that the output power of the BEFL has a threshold against the Brillouin pump power, and above the Brillouin threshold, the output power increases linearly with the EDFA pump power. The BEFL threshold decreases with increasing the length of the optical fiber in the laser resonator used as a Brillouin gain medium. The BEFL oscillates in a stable single longitudinal mode because the bandwidth of the Brillouin gain profile is very narrow ( 30 MHz). The relative intensity noise (RIN) and the spectral lineshape were measured. The noise floor level decreases with increasing the EDFA pump power, and the full-width at half maximum of the BEFL was measured to be about 8 kHz.

Coupled model of square spiral inductor is simplified in this work for the purpose of fast estimation of inductor performance. The inductor structure is divided into two coupled parallel multi-conductor networks without corner segments. Two-dimensional numerical method is applied to each network to extract its distributed parameters for network matrices calculation. Equivalent circuit is built after connecting the two networks. Verification with momentum and measurement results demonstrates the accuracy and scalability of this model.

Based on the periodical-loaded principle, a new wider stop-band filter is presented. The design equations are provided, the validity of which is proved by the measured results. Compared with loaded stub of length 1/4λ_g, the improved T-shape stub can change admittance paralleled with microstrip line and widen the band width of the band-stop filter. The size of the filter loaded by one side can be reduced by 2/3. The stop-band filter loaded by one side and two sides are simulated and realized. The filter loaded by two sides can achieve very wide stop-band. In addition, the stop-band of the new type of filter is deep and steep.

The conditional sum adder (CSA) has been shown to outperform other adders applied in high-speed applications. This investigation proposes a modified CSA called the conditional carry adder (CCA). Based on the proposed adder architecture, six 64-bit hybrid dual-threshold CCAs for power-aware applications were discussed. Architectural modification of the CCA raises the operation speed, decreases the power dissipation, and lowers the hardware overhead. The proposed 64-bit CCA can decrease the number of multiplexers and internal nodes in the adder design by around 27% compared to the 64-bit CSA. Furthermore, components on critical paths use a low threshold voltage to accelerate the speed of operation, and other components use the normal threshold voltage to save power. This feature is very useful in implementing power-aware arithmetic systems. One of the proposed circuits has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.

A signature-matching co-processor in 130 nm CMOS technology for application in the network-security field is presented. Two key search technologies, implemented with fully-parallel CAM-based search cores, enable the removal of misused packets from Giga-bit-per-second (G-bps) networks in real-time without disturbing the normal network traffic. The first technology is a thorough search through packet header as well as payload in byte-shifting manner and is capable of detecting viruses, even if they are hidden at an arbitrary position within the packet. A 1.125 Mbit ternary CAM, operated at the speed of 125 Mega-searches per second (M-sps), integrates the primary lookup table for thorough packet search. The second technology applies an additional relational search with programmable logical operations to detect recently appearing more complicated misused packets. A small 192-bit binary CAM operated at 31.25 M-sps is also included for this purpose. Power dissipation, being a major concern of CAM-based application-specific LSIs, is addressed in the light of the signature-matching application, which has a high probability of multiple matches and which doesn't require to mask individual bits of the search word. Consequently, two application-driven power-reduction methods are implemented, namely an improved pipelined search for efficiently reducing power even in the case of a large number of multiple matches, and a search-line encoding for cutting search-line related power dissipation. As a result the signature-matching co-processor features low power dissipation between 0.4 W and 1.1 W for the best case and the worst case search configurations, respectively.

The electrostatic discharge (ESD) effect in GMR heads in the deshunting process is studied in order to prevent the damage in this process. The simulation and experiment results are investigated and compared. It is found from these results that sequences of deshunting process, currently operating, can cause the damage of GMR heads due to the ESD effect, based on the charged device model, CDM. This also shows that the voltage across GMR head, as the tweezers is used, can be raised up to 3.7 V which is about harmful to damage the head. Examples of damage heads confirmed by the SEM are also shown.