A wide range CMOS voltage detector with low current consumption consisting of CMOS inverters operating in both weak inversion and saturation region is proposed. A terminal of power supply for CMOS inverter can be expanded to a signal input terminal. A voltage-detection point and hysteresis characteristics of the proposed circuit can be designed by geometrical factor in MOSFET and an external bias voltage. The core circuit elements are fabricated in standard 0.18 µm CMOS process and measured to confirm the operation. The detectable voltage is from 0.3 V to 1.8 V. The current consumption of voltage detection, standby current, is changed from 65 pA for Vin = 0.3 V to 5.5 µA for Vin = 1.8 V. The thermal characteristics from 250 K to 400 K are also considered. The measured temperature coefficient of the proposed voltage-detector core operating in weak inversion region is 4 ppm/K and that in saturation region is 10 ppm/K. The proposed voltage detector can be implemented with tiny chip area and is expected to an on-chip voltage detector of power supply for mobile application systems.

A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.

This paper proposes an improved type of the Hybrid-Parallel Power-Factor-Correction (HP-PFC) converter. It has the advantage of a higher efficiency and improved input current waveform. This advantage achieved through changing new charging path of the bulk capacitor and balancing the power flow from the two transformers to the output. This new circuit has been analyzed using MATLAB/Simulink and confirmed with experiment. As a conclusion, it is confirmed that this improved HP-PFC converter complies with the severe regulation of IEC61000-3-2 Class D. Moreover, a high efficiency of 90% is achieved for 15 V/6 A output power under the worldwide line voltage conditions.