A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip

Shoichiro KAWASHIMA; Isao FUKUSHI; Keizo MORITA; Ken-ichi NAKABAYASHI; Mitsuharu NAKAZAWA; Kazuaki YAMANE; Tomohisa HIRAYAMA; Toru ENDO

doi:10.1093/ietele/e90-c.10.1941

A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip

Shoichiro KAWASHIMA, Isao FUKUSHI, Keizo MORITA, Ken-ichi NAKABAYASHI, Mitsuharu NAKAZAWA, Kazuaki YAMANE, Tomohisa HIRAYAMA, Toru ENDO

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A robust 1T1C FeRAM sensing technique is demonstrated that employs both word base access and reference level generation architecture to track the thermal history of the cells by utilizing a Feedback inverter Input Push-down (FIP) method for a Bit line Ground Sensing (BGS) pre-amplifier and a self-timing latch Sense Amplifier (SA) which is immune to increasing non-switching charges due to thermal depolarization or imprint of ferroelectric capacitor. The word base access unit consists of one 2T2C cell that stores 0/1 data and also generates '0' and '1' reference levels by which other 1T1C signals are compared. A 0.18-µm CMOS 3-V 1-Mbit device was qualified by a 250 bake for a short time retention and 150 1000-hour bake which is an accelerated equivalent to 10-years retention. It endured 10¹² fatigue cycles with an access time of 81 ns, 3.0 V VDD at 85. Also a Smart Card application chip which is embedded with the 1-Mbit FeRAM macro showed 30% faster download time than one with EEPROM.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.10 pp.1941-1948

Publication Date: 2007/10/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.10.1941

Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)

Category: Next-Generation Memory for SoC

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Shoichiro KAWASHIMA, Isao FUKUSHI, Keizo MORITA, Ken-ichi NAKABAYASHI, Mitsuharu NAKAZAWA, Kazuaki YAMANE, Tomohisa HIRAYAMA, Toru ENDO, "A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 10, pp. 1941-1948, October 2007, doi: 10.1093/ietele/e90-c.10.1941.
Abstract: A robust 1T1C FeRAM sensing technique is demonstrated that employs both word base access and reference level generation architecture to track the thermal history of the cells by utilizing a Feedback inverter Input Push-down (FIP) method for a Bit line Ground Sensing (BGS) pre-amplifier and a self-timing latch Sense Amplifier (SA) which is immune to increasing non-switching charges due to thermal depolarization or imprint of ferroelectric capacitor. The word base access unit consists of one 2T2C cell that stores 0/1 data and also generates '0' and '1' reference levels by which other 1T1C signals are compared. A 0.18-µm CMOS 3-V 1-Mbit device was qualified by a 250 bake for a short time retention and 150 1000-hour bake which is an accelerated equivalent to 10-years retention. It endured 10¹² fatigue cycles with an access time of 81 ns, 3.0 V VDD at 85. Also a Smart Card application chip which is embedded with the 1-Mbit FeRAM macro showed 30% faster download time than one with EEPROM.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.10.1941/_p

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@ARTICLE{e90-c_10_1941,
author={Shoichiro KAWASHIMA, Isao FUKUSHI, Keizo MORITA, Ken-ichi NAKABAYASHI, Mitsuharu NAKAZAWA, Kazuaki YAMANE, Tomohisa HIRAYAMA, Toru ENDO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip},
year={2007},
volume={E90-C},
number={10},
pages={1941-1948},
abstract={A robust 1T1C FeRAM sensing technique is demonstrated that employs both word base access and reference level generation architecture to track the thermal history of the cells by utilizing a Feedback inverter Input Push-down (FIP) method for a Bit line Ground Sensing (BGS) pre-amplifier and a self-timing latch Sense Amplifier (SA) which is immune to increasing non-switching charges due to thermal depolarization or imprint of ferroelectric capacitor. The word base access unit consists of one 2T2C cell that stores 0/1 data and also generates '0' and '1' reference levels by which other 1T1C signals are compared. A 0.18-µm CMOS 3-V 1-Mbit device was qualified by a 250 bake for a short time retention and 150 1000-hour bake which is an accelerated equivalent to 10-years retention. It endured 10¹² fatigue cycles with an access time of 81 ns, 3.0 V VDD at 85. Also a Smart Card application chip which is embedded with the 1-Mbit FeRAM macro showed 30% faster download time than one with EEPROM.},
keywords={},
doi={10.1093/ietele/e90-c.10.1941},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip
T2 - IEICE TRANSACTIONS on Electronics
SP - 1941
EP - 1948
AU - Shoichiro KAWASHIMA
AU - Isao FUKUSHI
AU - Keizo MORITA
AU - Ken-ichi NAKABAYASHI
AU - Mitsuharu NAKAZAWA
AU - Kazuaki YAMANE
AU - Tomohisa HIRAYAMA
AU - Toru ENDO
PY - 2007
DO - 10.1093/ietele/e90-c.10.1941
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2007
AB - A robust 1T1C FeRAM sensing technique is demonstrated that employs both word base access and reference level generation architecture to track the thermal history of the cells by utilizing a Feedback inverter Input Push-down (FIP) method for a Bit line Ground Sensing (BGS) pre-amplifier and a self-timing latch Sense Amplifier (SA) which is immune to increasing non-switching charges due to thermal depolarization or imprint of ferroelectric capacitor. The word base access unit consists of one 2T2C cell that stores 0/1 data and also generates '0' and '1' reference levels by which other 1T1C signals are compared. A 0.18-µm CMOS 3-V 1-Mbit device was qualified by a 250 bake for a short time retention and 150 1000-hour bake which is an accelerated equivalent to 10-years retention. It endured 10¹² fatigue cycles with an access time of 81 ns, 3.0 V VDD at 85. Also a Smart Card application chip which is embedded with the 1-Mbit FeRAM macro showed 30% faster download time than one with EEPROM.
ER -