An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm2 is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm2[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm2, which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm2×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.

An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 1818 logic blocks and an area of 54.76 mm2.

A robust 1T1C FeRAM sensing technique is demonstrated that employs both word base access and reference level generation architecture to track the thermal history of the cells by utilizing a Feedback inverter Input Push-down (FIP) method for a Bit line Ground Sensing (BGS) pre-amplifier and a self-timing latch Sense Amplifier (SA) which is immune to increasing non-switching charges due to thermal depolarization or imprint of ferroelectric capacitor. The word base access unit consists of one 2T2C cell that stores 0/1 data and also generates '0' and '1' reference levels by which other 1T1C signals are compared. A 0.18-µm CMOS 3-V 1-Mbit device was qualified by a 250 bake for a short time retention and 150 1000-hour bake which is an accelerated equivalent to 10-years retention. It endured 1012 fatigue cycles with an access time of 81 ns, 3.0 V VDD at 85. Also a Smart Card application chip which is embedded with the 1-Mbit FeRAM macro showed 30% faster download time than one with EEPROM.

This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-µm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.

We have fabricated ferroelectric Pb(Zr,Ti)O3 (PZT) thin films using low-pressure consolidation process during the sol-gel method. Drastic improvements of electrical properties have been obtained for the PZT thin films fabricated with low-pressure consolidation process. A remanent polarization (Pr) of 37 µC/cm2 and a coercive field (EC) of 64 kV/cm have been achieved. In addition, the leakage current of the PZT films fabricated using low-pressure consolidation is 102 times smaller than that of the films fabricated with the usual process of sol-gel method. It is also found that the low-pressure consolidation process is effective on improvements of electrical properties of PZT films fabricated at lower crystallization temperatures and with sub-100 nm thickness.

A chain ferroelectric random-access memory (chain FeRAM) is a solution for future high-density and high-speed nonvolatile memory. One memory cell consists of one transistor and one ferroelectric capacitor connected in parallel, and one memory cell block consists of plural cells and a block selecting transistor in series. This configuration realizes small memory cell of 4F2 size and fast random access time. This paper shows an overview and trend of chain FeRAM architecture. First, the concept of chain FeRAM is presented, and basic operations including two cell-plate driving schemes are discussed. Second, assuming multi-megabit generation, ideal features and performances are discussed in terms of die size, speed and other aspects. Third, the prototype of chain FeRAM and the practical cell structure for megabit-scale memories using 0.5 µ m 2-metal CMOS process are demonstrated. By introducing fast and compact cell-plate drive technique, this prototype achieves random access time of 37-ns and read/write cycle time of 80-ns, which are the fastest speeds reported for FeRAMs. Fourth, after discussing future memory cell trend and problems respecting scaled FeRAMs, a gain cell block approach for future gigabit-scale chain FeRAMs is introduced. This realizes both a small average cell size and a large cell signal even at small cell polarization.

Effects of imprint on signal margin in FeRAM with Pt/SrBi2Ta2O9/Pt capacitors have been investigated. Imprint, induced during high temperature storage, significantly reduced the signal margin and hence determines lifetime of FeRAM. Initial signal margin of 470 mV is reduced to 290 mV after storage at 175C for 96 hours. From the reduction rate of the signal margin, it is estimated that imprint lifetime of the FeRAM is more than 10 years even though the storage temperature is 175C.

We have constructed Bi based layer structured ferroelectric films and their superlattices by a pulsed laser deposition technique. The dielectric constants along c-axis increase with increasing of the number of pseudo-perovskite layers between double Bi2O2 layers. Ferroelectricity appears along the c-axis direction only for the odd number of the perovskite layers owing to the mirror symmetry in a crystal structure. Especially, the Bi2VO5. 5 film shows an atomically flat surface, low dielectric constant of 30 and ferroelectricity of Pr=3 µC/cm2 and Ec=16 kV/cm, respectively. This material is expected to the application for FRAMs.

Ferroelectric non-volatile memory (FeRAM) has been inspiring interests since bismuth layer perovskite material family was found to provide "Fatigue Free" endurance, superior retention and imprint characteristics. In this paper, we will provide new circuits technology for FeRAM developed to implement high speed operation, low voltage operation and low power consumption. Performance of LSI embedded with FeRAM for contactless IC card is also provided to demonstrate the feasibility of the circuit technology.

Ferroelectic nonvolatile technology comprises the ferroelectric material technology, the process technology and the circuit technology. Bi based layered Perovskyte ferroelectric material, SrBi2Ta2O9, so called "Y 1," has superior characteristics in terms of endurance and nonvolatile properties, which is confirmed by a 256kbit ferroelectric nonvolatile memory. Critical issues regarding the ferroelectric process are reviewed. The lT/lC cell configuration which is essential for a high density memory and the reference voltage generator employed in the 256 k memory are described as is the architecture to reduce the power consumption of the memory.