A 2-Mb 1T1C FeRAM Prototype Based on PMOS-Gating Cell Structure

Yeonbae CHUNG; Jung-Hyun KIM; Jae-Eun YOON

A 2-Mb 1T1C FeRAM Prototype Based on PMOS-Gating Cell Structure

Yeonbae CHUNG, Jung-Hyun KIM, Jae-Eun YOON

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This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) V_DD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-µm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.10 pp.1686-1693

Publication Date: 2004/10/01

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Type of Manuscript: Special Section PAPER (Special Section on New Era of Nonvolatile Memories)

Category: Ferroelectric Memory

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Yeonbae CHUNG, Jung-Hyun KIM, Jae-Eun YOON, "A 2-Mb 1T1C FeRAM Prototype Based on PMOS-Gating Cell Structure" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 10, pp. 1686-1693, October 2004, doi: .
Abstract: This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) V_DD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-µm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_10_1686/_p

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@ARTICLE{e87-c_10_1686,
author={Yeonbae CHUNG, Jung-Hyun KIM, Jae-Eun YOON, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 2-Mb 1T1C FeRAM Prototype Based on PMOS-Gating Cell Structure},
year={2004},
volume={E87-C},
number={10},
pages={1686-1693},
abstract={This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) V_DD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-µm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - A 2-Mb 1T1C FeRAM Prototype Based on PMOS-Gating Cell Structure
T2 - IEICE TRANSACTIONS on Electronics
SP - 1686
EP - 1693
AU - Yeonbae CHUNG
AU - Jung-Hyun KIM
AU - Jae-Eun YOON
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2004
AB - This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) V_DD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-µm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.
ER -