IEICE TRANSACTIONS on Electronics
A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
Summary :
An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.548-556
- Publication Date
- 2011/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.548
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
- Category
Authors
Masahiro IIDA
Masahiro KOGA
Kazuki INOUE
Motoki AMAGASAKI
Yoshinobu ICHIDA
Mitsuro SAJI
Jun IIDA
Toshinori SUEYOSHI
Keyword
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Masahiro IIDA, Masahiro KOGA, Kazuki INOUE, Motoki AMAGASAKI, Yoshinobu ICHIDA, Mitsuro SAJI, Jun IIDA, Toshinori SUEYOSHI, "A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 548-556, April 2011, doi: 10.1587/transele.E94.C.548.
Abstract: An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.548/_p
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@ARTICLE{e94-c_4_548,
author={Masahiro IIDA, Masahiro KOGA, Kazuki INOUE, Motoki AMAGASAKI, Yoshinobu ICHIDA, Mitsuro SAJI, Jun IIDA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells},
year={2011},
volume={E94-C},
number={4},
pages={548-556},
abstract={An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18
keywords={},
doi={10.1587/transele.E94.C.548},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
T2 - IEICE TRANSACTIONS on Electronics
SP - 548
EP - 556
AU - Masahiro IIDA
AU - Masahiro KOGA
AU - Kazuki INOUE
AU - Motoki AMAGASAKI
AU - Yoshinobu ICHIDA
AU - Mitsuro SAJI
AU - Jun IIDA
AU - Toshinori SUEYOSHI
PY - 2011
DO - 10.1587/transele.E94.C.548
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18
ER -
English
