IEICE TRANSACTIONS on Electronics
18-GHz Clock Distribution Using a Coupled VCO Array
Summary :
This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.811-822
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.811
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
- Analog and Communications
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Takayuki SHIBASAKI, Hirotaka TAMURA, Kouichi KANDA, Hisakatsu YAMAGUCHI, Junji OGAWA, Tadahiro KURODA, "18-GHz Clock Distribution Using a Coupled VCO Array" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 811-822, April 2007, doi: 10.1093/ietele/e90-c.4.811.
Abstract: This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.811/_p
Copy
@ARTICLE{e90-c_4_811,
author={Takayuki SHIBASAKI, Hirotaka TAMURA, Kouichi KANDA, Hisakatsu YAMAGUCHI, Junji OGAWA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={18-GHz Clock Distribution Using a Coupled VCO Array},
year={2007},
volume={E90-C},
number={4},
pages={811-822},
abstract={This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.},
keywords={},
doi={10.1093/ietele/e90-c.4.811},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - 18-GHz Clock Distribution Using a Coupled VCO Array
T2 - IEICE TRANSACTIONS on Electronics
SP - 811
EP - 822
AU - Takayuki SHIBASAKI
AU - Hirotaka TAMURA
AU - Kouichi KANDA
AU - Hisakatsu YAMAGUCHI
AU - Junji OGAWA
AU - Tadahiro KURODA
PY - 2007
DO - 10.1093/ietele/e90-c.4.811
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the clock is generated by a one-dimensional VCO array in which the oscillating nodes of adjacent VCOs are directly connected with wires. The effects of the wire length and number of unit VCOs in the array are discussed. Both 4-unit and a 2-unit VCO arrays for delivering a clock signal to a 16:1 multiplexor were designed and fabricated in a 90-nm CMOS process. The frequency range of the 4-unit VCO array was 16 GHz to 18.5 GHz while each unit VCO consumed 2 mA.
ER -
English
