IEICE TRANSACTIONS on Electronics
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array
Summary :
The delay time (tdT), power dissipation (PT) and circuit volume of a CMOS register array were minimized. Seven test circuits, each of which had a register array and a single clock tree that generated a pair of complement clock pulses, and a conventional register were fabricated using 90-nm CMOS technology. The register array was constructed with M delay flip-flops (FFs) and the clock tree, which consisted of 2 driver stages. Each driver stage had m inverters, each of which drove M/m FFs where M was fixed at 40 and m varied from 1 to 40. The minimum values of tdT and PT were 0.25 ns and 17.88 µW, respectively, and were both obtained when m was 10. These values were 71.4% and 70.4% of tdT and PT for the conventional register, for which m is 40, respectively. The number of inverters in the clock tree when m was 10 was 21 which was only 25.9% that for the conventional register. The measured results agreed well with SPICE-simulated results. Furthermore, for values of M from 20 to 320, both the minimum tdT and the minimum PT were obtained when m was approximately 1.5 times the square root of M.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.4 pp.553-561
- Publication Date
- 2008/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.4.553
- Type of Manuscript
- Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
- Category
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Tadayoshi ENOMOTO, Suguru NAGAYAMA, Hiroaki SHIKANO, Yousuke HAGIWARA, "Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 4, pp. 553-561, April 2008, doi: 10.1093/ietele/e91-c.4.553.
Abstract: The delay time (tdT), power dissipation (PT) and circuit volume of a CMOS register array were minimized. Seven test circuits, each of which had a register array and a single clock tree that generated a pair of complement clock pulses, and a conventional register were fabricated using 90-nm CMOS technology. The register array was constructed with M delay flip-flops (FFs) and the clock tree, which consisted of 2 driver stages. Each driver stage had m inverters, each of which drove M/m FFs where M was fixed at 40 and m varied from 1 to 40. The minimum values of tdT and PT were 0.25 ns and 17.88 µW, respectively, and were both obtained when m was 10. These values were 71.4% and 70.4% of tdT and PT for the conventional register, for which m is 40, respectively. The number of inverters in the clock tree when m was 10 was 21 which was only 25.9% that for the conventional register. The measured results agreed well with SPICE-simulated results. Furthermore, for values of M from 20 to 320, both the minimum tdT and the minimum PT were obtained when m was approximately 1.5 times the square root of M.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.4.553/_p
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@ARTICLE{e91-c_4_553,
author={Tadayoshi ENOMOTO, Suguru NAGAYAMA, Hiroaki SHIKANO, Yousuke HAGIWARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array},
year={2008},
volume={E91-C},
number={4},
pages={553-561},
abstract={The delay time (tdT), power dissipation (PT) and circuit volume of a CMOS register array were minimized. Seven test circuits, each of which had a register array and a single clock tree that generated a pair of complement clock pulses, and a conventional register were fabricated using 90-nm CMOS technology. The register array was constructed with M delay flip-flops (FFs) and the clock tree, which consisted of 2 driver stages. Each driver stage had m inverters, each of which drove M/m FFs where M was fixed at 40 and m varied from 1 to 40. The minimum values of tdT and PT were 0.25 ns and 17.88 µW, respectively, and were both obtained when m was 10. These values were 71.4% and 70.4% of tdT and PT for the conventional register, for which m is 40, respectively. The number of inverters in the clock tree when m was 10 was 21 which was only 25.9% that for the conventional register. The measured results agreed well with SPICE-simulated results. Furthermore, for values of M from 20 to 320, both the minimum tdT and the minimum PT were obtained when m was approximately 1.5 times the square root of M.},
keywords={},
doi={10.1093/ietele/e91-c.4.553},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array
T2 - IEICE TRANSACTIONS on Electronics
SP - 553
EP - 561
AU - Tadayoshi ENOMOTO
AU - Suguru NAGAYAMA
AU - Hiroaki SHIKANO
AU - Yousuke HAGIWARA
PY - 2008
DO - 10.1093/ietele/e91-c.4.553
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2008
AB - The delay time (tdT), power dissipation (PT) and circuit volume of a CMOS register array were minimized. Seven test circuits, each of which had a register array and a single clock tree that generated a pair of complement clock pulses, and a conventional register were fabricated using 90-nm CMOS technology. The register array was constructed with M delay flip-flops (FFs) and the clock tree, which consisted of 2 driver stages. Each driver stage had m inverters, each of which drove M/m FFs where M was fixed at 40 and m varied from 1 to 40. The minimum values of tdT and PT were 0.25 ns and 17.88 µW, respectively, and were both obtained when m was 10. These values were 71.4% and 70.4% of tdT and PT for the conventional register, for which m is 40, respectively. The number of inverters in the clock tree when m was 10 was 21 which was only 25.9% that for the conventional register. The measured results agreed well with SPICE-simulated results. Furthermore, for values of M from 20 to 320, both the minimum tdT and the minimum PT were obtained when m was approximately 1.5 times the square root of M.
ER -
English
