IEICE TRANSACTIONS on Electronics
Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM
Summary :
The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.3 pp.436-442
- Publication Date
- 1997/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on SOI Devices and Their Process Technologies)
- Category
- Circuit Technologies and Applications
Authors
Keyword
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Akihiko YASUOKA, Kazutami ARIMOTO, "Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 3, pp. 436-442, March 1997, doi: .
Abstract: The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_3_436/_p
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@ARTICLE{e80-c_3_436,
author={Akihiko YASUOKA, Kazutami ARIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM},
year={1997},
volume={E80-C},
number={3},
pages={436-442},
abstract={The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 436
EP - 442
AU - Akihiko YASUOKA
AU - Kazutami ARIMOTO
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1997
AB - The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.
ER -
English
