The advantage of SOI wafers for device manufacture has been widely studied. To be a real challenger to bulk silicon, SOI producers have to offer SOI wafers in large volume and at low cost. The new Smart-Cut(R) SOI process used for the manufacture of the Unibond(R) SOI wafers answers most of the SOI wafer manufacturability issues. The use of Hydrogen implantation and wafer bonding technology is the best combination to get good uniformity and high quality for both the SOI and buried oxide layer. In this paper, the Smart-Cut(R) process is described in detail and material characteristics of Unibond(R) wafers such as crystalline quality, surface roughness, thin film thickness homogeneity, and electric behavior.

This paper reviews the structure and electrical properties of high-quality Internal Thermal OXidation (ITOX)-processed low-dose Separation by IMplanted OXygen (SIMOX) wafers. The ITOX SIMOX process consists of three steps: low-dose oxygen implantation, high-temperature annealing, and high-temperature oxidation. The low dose makes possible a high-throughput production of SIMOX wafers. The high-temperature annealing provides a continuous buried oxide layer and reduces the dislocation density in the top silicon layer. The subsequent high-temperature oxidation thickens the buried oxide layer without any additional oxygen implantation, thus improving its electrical properties. The ITOX mechanism is also described. It is concluded that the ITOX SIMOX wafers are very useful for fabricating ULSIs.

For bonded SOI wafers with active silicon layers thinner than 1 µm, controlling thickness uniformity of active layers has been developed recently. A Plasma Assisted Chemical Etching (PACE) technology is one of methods to realize 0.1 µm bonded SOI. When this technology was proposed for the first time, it was believed that 0.1 µm thick bonded SOI wafers were easily produced independent of initial SOI layer thickness prior to the PACE process. It was true to create 0.1 µm SOI thickness in average. However, the uniformity appeared to be dependent on initial SOI material as well as the PACE machine capability itself. The SOI thickness uniformity pattern after PACE looked like surface morphology of polished silicon wafers. After the experiment to apply various polishing methods to each polishing process in the bonded SOI process, it was verified that the final SOI thickness uniformity after the PACE process was dependent on the waviness of wafer surfaces created in polishing.

The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

Physical models for fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs are overviewed, and recent applications of them (in SOISPICE) are described, stressing the need for good physics-based accounting for the inherently coupled bipolar and MOS device features in reliable circuit design. The applications suggest that asymmetrical double-gate FD/SOI CMOS technology can be scaled below 0.1 µm, whereas the single-gate counterpart seemingly cannot be, and that the floating-body charge dynamics and the associated transient leakage current in NFD/SOI (and FD/SOI) pass transistors in memory (DRAM and SRAM) circuits can be effectively controlled by optimal device design.

This paper describes what happens when the silicon layer is extremely thinned. The discussion shows that quantum mechanical short-channel effects impose limits on the down-scaling of MOSFET/SOI devices. However, thinning the silicon layer should bring new possibilities such as mobility enhancement, velocity overshoot enhancement, suppression of band-to-band tunneling, suppression of impact ionization and so on. Furthermore, the non-stationary energy transport in extremely miniaturized ultra-thin MOSFET/SOI devices is also addressed from the viewpoint of hot-carrier immunity. Related device physics are also discussed in order to consider the design methodology for contemporary MOSFET/SOI devices and new device applications for the future.

A 0.35 µm CMOS process for low-voltage, high-performance applications implemented in an ultra-thin-film SIMOX wafer: Shallow SIMOX, is described. Fully Depleted CMOS devices are realized in a 50 nm thick top Si film. Stable high speed, low-Vth transistors for low-voltage operation were developed by integrating a salicided dual gate process. Short-channel effects are suppressed by a novel channel-drain profile engineering. Low power consumption is achieved by the reduced diffusion capacitance of the SIMOX device and a thick, CMP planarized, intermetal dielectric to reduce metal interconnect capacitance's. Compared with the Bulk-Si CMOS devices, a factor of 1/5 reduction on power dissipation is achieved with this technology. A high ESD strength of 4 kV (HBM) demonstrates the applicability of this technology in advanced high-performance products.

Heavy-ion-induced soft errors (single event upset) in submicron silicon-on-insulator (SOI) MOSFETs under space environmental conditions are studied over the temperature range of 100-400 K using three-dimensional device simulator with full-temperature models. The temperature dependence of the drain collected charge is examined in detail when a heavy-ion strikes the gate center perpendicularly. At very low temperatures, SOI MOSFETs have very high immunity to the heavy-ion-induced soft errors. In particular, alpha-particle-induced soft errors hardly occur at temperatures below 200 K. As the temperature increases, the collected charge shows a marked rate of increase. The problem of single event upset in SOI MOSFETs becomes more serious with increasing working temperature. This is because the induced bipolar mechanism is a main factor to cause charge collection in SOI MOSFETs and the bipolar current increases exponentially with increasing temperature. At room and high temperatures, the drain collected charge is strongly dependent on channel length and SOI film thickness.

This paper describes an analytic method, experimental results and simulation results for self-heating in a SOI (Silicon On Insulator) high voltage MOS transistor. The new analytic method enabled the temperature-rise caused by self-heating to be measured precisely. The temperature-rise in an operating transistor was evaluated by measuring the change of the source current against the source current without the self-heating. In advance, the relation between the temperature-rise and the current change had been prepared by measuring the current decrease when the hot-chuck temperature had been changed in iso-thermal condition. By using this method, the dependence of the temperature-rise or the current decrease on the operating condition or the thermal resistance were clarified. Furthermore, these measurement results and the thermal resistance which is calculated by a FEM analysis enabled a fully coupled electrothermal device simulation to be analyzed more precisely. The dependence of the current decrease on the buried oxide thickness were also calculated.

The parasitic bipolar effect in a 200-V-class thin-film SOI power MOSFET fabricated using the silicon wafer direct bonding wafer was investigated by electrical measurement, two-dimensional process simulation, emission microscopy, and 2-dimensional thermal analysis. It degraded the breakdown voltage of the thin-film SOI power MOSFET and was caused by the increase in the sheet resistance of the body contact region. Photo emission analysis indicated that excess holes recombined in the n⁺-source region.

The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.

For low-voltage, high-speed operation of LSIs, the most attractive features in fully-depleted (FD) SOI devices are their steep subthreshold slope and reduced drain junction capacitance. This paper discusses the impact of these features on circuit performance. FD SOI devices can have a threshold voltage of more than 100 mV lower than that of bulk devices within the limits of acceptable off-state leakage current. Thus they hold higher driving current even at supply voltages of less than 1 V. On the other hand, the reduced junction capacitance is effective to suppress the total parasitic capacitance especially in lightly loaded CMOS circuits. These attractive features improve the speed performance in FD SOI circuits remarkably at supply voltages of less than 1 V. For high-speed circuit applications, 0.25-µm-gate SIMOX circuits, such as frequency dividers, prescalers, MUX, and DEMUX, can operate at up to 1-2 GHz even at a supply voltage of 1 V. CMOS/SIMOX logic LSIs also exhibit better performance at very low supply voltages. At merely 1 V, a SIMOX logic LSI could be functional at up to 60-90 MHz using 0.26-0.34 µW/MHz/Gate of power dissipation. Furthermore, SIMOX logic LSIs will allow 20-30 MHz operation at 0.5 V of a solar cell with reasonable chip size. These investigations lead to the conclusion that FD CMOS/SIMOX technology will have a large impact on the development of low-voltage high-performance LSIs for portable digital equipment and telecommunication systems.

In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1 V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption without additional circuits. An LSI architecture featuring a low supply voltage for internal gates and an LVTTL interface is proposed. However, to implement the architecture with FD-CMOS/SIMOX devices, there were problems which were low drain-breakdown voltage and half electrostatic discharge (ESD) hardness compared with that of bulk CMOS devices. An LVTTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output stage and a voltage converter with cross-coupled PMOS is used for reducing the applied voltage from 3.3 V to 2.2 V or less. Using this output buffer together with an LVTTL-compatible input buffer, external 3.3 V signal can be converted from/to 2.0-1.2 V signal with little static current. The cascade circuit, however, weakens the already low ESD hardness of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes working as drain-well-diodes in bulk CMOS and protection devices for dual power supplies. A diode/MOS merged layout pattern is used for both to dissipate heat and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-µm CMOS/SIMOX, 0.25-µm bulk CMOS and 0.5-µm bulk CMOS, power consumptions are compared. The 0.25-µm CMOS/SIMOX LSI can operate at an internal voltage of 1.2 V at the same frequency as the 0.5-µm LSI operating at 3.3 V. The internal supply voltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-µm bulk LVTTL-LSI.

A high-speed silicon-on-insulator (SOI) of a 1/8 frequency divider and a 64-bit adder were realized using an optimized gate-overlapped LDD and a self-aligned titanium silicide (TiSi₂) source-drain structure. The advantages of the delay time and power consumption were analyzed by circuit simulation. The maximum operation frequency of the SOI divider is 2.9 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than the bulk-Si divider. The power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. On the other hand, the speed of the SOI adder is 1.9 nsec at 3.3 V. The SOI adder speed is about 1.3 times faster than the bulk adder. The power consumption of the SOI adder is about 80% of that of the bulk divider. It was found that the high speed, low power features of the SOI divider were due to the pass transistor which had low junction capacitance and little substrate bias effects, in addition to the low wiring capacitance and low fanout capacitance compared to the bulk adder. As a result, it is suggested that SOI circuits using pass transistor have a potential for GHz level systems and it is expected they will be applied to handy communication systems and portable computers used in the multimedia era.

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was discussed in previous work [1]. RPL combines advantages of both the compact size of CPL and the full voltage-swing of DPL, and gives reasonably high performance concerning both speed and power consumption. In this paper, the application and design technique of RPL on larger logic circuits and systems are reported. Parallel adders and Booth multipliers with different sizes and structures are used as examples to evaluate the functionality of the RPL gates and full adder. In addition, there is less signal skew in RPL circuits than in conventional CPL circuits when an arrangement of single-rail to dual-rail signal conversion is performed. And, RPL is found to be useful in design of high speed and high density parallel adders and multipliers.

We developed a 1200 dots-per-inch light emitting diode array (1200 dpi LED array) chip using a GaAs_0.8 P_0.2 epitaxial substrate for the first time. One LED array chip consists of 256 LEDs. In general, LED arrays are fabricated by vapor-phase zinc diffusion. From the viewpoint that shallow junctions should be formed to fabricate a very high-density LED array, solid-phase diffusion seems to be more suitable. We fabricated the LED array using selectively-masked solid-phase zinc diffusion, and the diffusion depth was controlled at 1 µm. The diffusion depth was uniform under the diffusion window. The ratio of the length of lateral diffusion to the diffusion depth was about 1.7. These features imply that Zn diffusion was well controlled. In the Zn diffusion, the carrier concentration in the Zn diffusion region was high enough and the sheet resistance of the diffusion region with a diffusion depth of 1 µm was low enough to obtain a sufficient level of emitted light power. The results of performance tests showed that the characteristics of the LED array chip are satisfactory for application in optical printer print heads, because of the array's highly-resolved near-field pattern characteristic, ample emitted light power, low emitted-light-power deviation, and long life.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

The applicability of a boundary matching technique is presented for reconstructing the refractive-index profile of a circularly symmetric cylinder from the measurement of the scattered wave when the cylinder is illuminated by an H-polarized plane wave. The algorithm of reconstruction is based on an iterative procedure of matching the scattered wave calculated from a certain refractive-index distribution with the measured scattered-wave. The limits of reconstruction for strongly inhomogeneous lossless and lossy cylinders are numerically shown through computer simulations under noisy environment, and are compared with those in the E-wave case.