High-Frequency, Low-Noise Si Bipolar Transistor Fabricated Using Self-Aligned Metal/IDP Technology

Hiromi SHIMAMOTO; Takahiro ONAI; Eiji OHUE; Masamichi TANABE; Katsuyoshi WASHIO

High-Frequency, Low-Noise Si Bipolar Transistor Fabricated Using Self-Aligned Metal/IDP Technology

Hiromi SHIMAMOTO, Takahiro ONAI, Eiji OHUE, Masamichi TANABE, Katsuyoshi WASHIO

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A high-frequency, low-noise silicon bipolar transistor that can be used in over-10 Gb/s optical communication systems and wireless communication systems has been developed. The silicon bipolar transistor was fabricated using self-aligned metal/IDP (SMI) technology, which produces a self-aligned base electrode of stacked layers of metal and in-situ doped poly-Si (IDP) by low-temperature selective tungsten CVD. It provides a low base resistance and high-cutoff frequency. The base resistance is reduced to half that of a transistor with a conventional poly-Si base electrode. By using the SMI technology and optimizing the depth of the emitter and the link base, we achieved the maximum oscillation frequency of 80 GHz, a minimum gate delay in an ECL of 11.6 ps, and the minimum noise figure of 0.34 dB at 2 GHz, which are the highest performances among those obtained from ion-implanted base Si bipolar transistors, and are comparable to those of SiGe base heterojunction bipolar transistors.

Publication: IEICE TRANSACTIONS on Electronics Vol.E82-C No.11 pp.2007-2012

Publication Date: 1999/11/25

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Type of Manuscript: Special Section PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century)

Category: Low Power-Consumption RF ICs

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Hiromi SHIMAMOTO, Takahiro ONAI, Eiji OHUE, Masamichi TANABE, Katsuyoshi WASHIO, "High-Frequency, Low-Noise Si Bipolar Transistor Fabricated Using Self-Aligned Metal/IDP Technology" in IEICE TRANSACTIONS on Electronics, vol. E82-C, no. 11, pp. 2007-2012, November 1999, doi: .
Abstract: A high-frequency, low-noise silicon bipolar transistor that can be used in over-10 Gb/s optical communication systems and wireless communication systems has been developed. The silicon bipolar transistor was fabricated using self-aligned metal/IDP (SMI) technology, which produces a self-aligned base electrode of stacked layers of metal and in-situ doped poly-Si (IDP) by low-temperature selective tungsten CVD. It provides a low base resistance and high-cutoff frequency. The base resistance is reduced to half that of a transistor with a conventional poly-Si base electrode. By using the SMI technology and optimizing the depth of the emitter and the link base, we achieved the maximum oscillation frequency of 80 GHz, a minimum gate delay in an ECL of 11.6 ps, and the minimum noise figure of 0.34 dB at 2 GHz, which are the highest performances among those obtained from ion-implanted base Si bipolar transistors, and are comparable to those of SiGe base heterojunction bipolar transistors.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_11_2007/_p

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@ARTICLE{e82-c_11_2007,
author={Hiromi SHIMAMOTO, Takahiro ONAI, Eiji OHUE, Masamichi TANABE, Katsuyoshi WASHIO, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Frequency, Low-Noise Si Bipolar Transistor Fabricated Using Self-Aligned Metal/IDP Technology},
year={1999},
volume={E82-C},
number={11},
pages={2007-2012},
abstract={A high-frequency, low-noise silicon bipolar transistor that can be used in over-10 Gb/s optical communication systems and wireless communication systems has been developed. The silicon bipolar transistor was fabricated using self-aligned metal/IDP (SMI) technology, which produces a self-aligned base electrode of stacked layers of metal and in-situ doped poly-Si (IDP) by low-temperature selective tungsten CVD. It provides a low base resistance and high-cutoff frequency. The base resistance is reduced to half that of a transistor with a conventional poly-Si base electrode. By using the SMI technology and optimizing the depth of the emitter and the link base, we achieved the maximum oscillation frequency of 80 GHz, a minimum gate delay in an ECL of 11.6 ps, and the minimum noise figure of 0.34 dB at 2 GHz, which are the highest performances among those obtained from ion-implanted base Si bipolar transistors, and are comparable to those of SiGe base heterojunction bipolar transistors.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - High-Frequency, Low-Noise Si Bipolar Transistor Fabricated Using Self-Aligned Metal/IDP Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 2007
EP - 2012
AU - Hiromi SHIMAMOTO
AU - Takahiro ONAI
AU - Eiji OHUE
AU - Masamichi TANABE
AU - Katsuyoshi WASHIO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1999
AB - A high-frequency, low-noise silicon bipolar transistor that can be used in over-10 Gb/s optical communication systems and wireless communication systems has been developed. The silicon bipolar transistor was fabricated using self-aligned metal/IDP (SMI) technology, which produces a self-aligned base electrode of stacked layers of metal and in-situ doped poly-Si (IDP) by low-temperature selective tungsten CVD. It provides a low base resistance and high-cutoff frequency. The base resistance is reduced to half that of a transistor with a conventional poly-Si base electrode. By using the SMI technology and optimizing the depth of the emitter and the link base, we achieved the maximum oscillation frequency of 80 GHz, a minimum gate delay in an ECL of 11.6 ps, and the minimum noise figure of 0.34 dB at 2 GHz, which are the highest performances among those obtained from ion-implanted base Si bipolar transistors, and are comparable to those of SiGe base heterojunction bipolar transistors.
ER -