A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive
Summary :
A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E82-C No.9 pp.1777-1779
- Publication Date
- 1999/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Integrated Electronics
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Jin-Cheon KIM, Sang-Hoon LEE, Hong-June PARK, "A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1777-1779, September 1999, doi: .
Abstract: A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1777/_p
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@ARTICLE{e82-c_9_1777,
author={Jin-Cheon KIM, Sang-Hoon LEE, Hong-June PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive},
year={1999},
volume={E82-C},
number={9},
pages={1777-1779},
abstract={A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.},
keywords={},
doi={},
ISSN={},
month={September},}
Copy
TY - JOUR
TI - A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive
T2 - IEICE TRANSACTIONS on Electronics
SP - 1777
EP - 1779
AU - Jin-Cheon KIM
AU - Sang-Hoon LEE
AU - Hong-June PARK
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.
ER -
English
