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Young-Su KWON In-Cheol PARK Chong-Min KYUNG
A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. Vcc is supplied to the random logic circuits and flip-flops while Vcc/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.
Jin-Cheon KIM Sang-Hoon LEE Hong-June PARK
A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.