IEICE TRANSACTIONS on Electronics
CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip
Summary :
A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V-programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 µ m CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.6 pp.734-739
- Publication Date
- 2001/06/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Nonvolatile Memories)
- Category
- Flash Memories
Authors
Keyword
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Shoji SHUKURI, Kazumasa YANAGISAWA, Koichiro ISHIBASHI, "CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 6, pp. 734-739, June 2001, doi: .
Abstract: A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V-programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 µ m CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_6_734/_p
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@ARTICLE{e84-c_6_734,
author={Shoji SHUKURI, Kazumasa YANAGISAWA, Koichiro ISHIBASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip},
year={2001},
volume={E84-C},
number={6},
pages={734-739},
abstract={A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V-programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 µ m CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - CMOS Process Compatible ie-Flash (Inverse Gate Electrode Flash) Technology for System-on-a Chip
T2 - IEICE TRANSACTIONS on Electronics
SP - 734
EP - 739
AU - Shoji SHUKURI
AU - Kazumasa YANAGISAWA
AU - Koichiro ISHIBASHI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2001
AB - A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in a standard CMOS process without any process modifications, has been developed. The ie-flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V-programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 µ m CMOS process is demonstrated. This flash technology will extends not only testing cost reduction of the system-on-a chip by replacing laser-link but also provides flexibility of programmable logic applications.
ER -
English
