Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems

Takashi YAMADA; Shoji GOTO; Norihisa TAKAYAMA; Yoshifumi MATSUSHITA; Yasoo HARADA; Hiroto YASUURA

Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems

Takashi YAMADA, Shoji GOTO, Norihisa TAKAYAMA, Yoshifumi MATSUSHITA, Yasoo HARADA, Hiroto YASUURA

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In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power Digital Matched Filter (DMF) for the direct-sequence spread-spectrum communication system such as WCDMA or wireless LAN. The proposed approach for power savings focuses on the architecture of the reception registers and the correlation-calculating unit, which dissipate the majority of the power in a DMF. The main features are asynchronous latch clock generation for the reception registers, parallelism of correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the WCDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-µm CMOS standard cell array technology. As a result, the power consumption of the proposed DMF is estimated to be 9.3 mW (@15.6 MHz, 1.6 V), which is below 40% of the power consumed by a general DMF.

Publication: IEICE TRANSACTIONS on Electronics Vol.E86-C No.1 pp.79-88

Publication Date: 2003/01/01

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Takashi YAMADA, Shoji GOTO, Norihisa TAKAYAMA, Yoshifumi MATSUSHITA, Yasoo HARADA, Hiroto YASUURA, "Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems" in IEICE TRANSACTIONS on Electronics, vol. E86-C, no. 1, pp. 79-88, January 2003, doi: .
Abstract: In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power Digital Matched Filter (DMF) for the direct-sequence spread-spectrum communication system such as WCDMA or wireless LAN. The proposed approach for power savings focuses on the architecture of the reception registers and the correlation-calculating unit, which dissipate the majority of the power in a DMF. The main features are asynchronous latch clock generation for the reception registers, parallelism of correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the WCDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-µm CMOS standard cell array technology. As a result, the power consumption of the proposed DMF is estimated to be 9.3 mW (@15.6 MHz, 1.6 V), which is below 40% of the power consumed by a general DMF.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_1_79/_p

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@ARTICLE{e86-c_1_79,
author={Takashi YAMADA, Shoji GOTO, Norihisa TAKAYAMA, Yoshifumi MATSUSHITA, Yasoo HARADA, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems},
year={2003},
volume={E86-C},
number={1},
pages={79-88},
abstract={In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power Digital Matched Filter (DMF) for the direct-sequence spread-spectrum communication system such as WCDMA or wireless LAN. The proposed approach for power savings focuses on the architecture of the reception registers and the correlation-calculating unit, which dissipate the majority of the power in a DMF. The main features are asynchronous latch clock generation for the reception registers, parallelism of correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the WCDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-µm CMOS standard cell array technology. As a result, the power consumption of the proposed DMF is estimated to be 9.3 mW (@15.6 MHz, 1.6 V), which is below 40% of the power consumed by a general DMF.},
keywords={},
doi={},
ISSN={},
month={January},}

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TY - JOUR
TI - Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 79
EP - 88
AU - Takashi YAMADA
AU - Shoji GOTO
AU - Norihisa TAKAYAMA
AU - Yoshifumi MATSUSHITA
AU - Yasoo HARADA
AU - Hiroto YASUURA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2003
AB - In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power Digital Matched Filter (DMF) for the direct-sequence spread-spectrum communication system such as WCDMA or wireless LAN. The proposed approach for power savings focuses on the architecture of the reception registers and the correlation-calculating unit, which dissipate the majority of the power in a DMF. The main features are asynchronous latch clock generation for the reception registers, parallelism of correlation calculation operations and bit manipulation for chip-correlation operations. A DMF is designed in compliance with the WCDMA specifications incorporating the proposed techniques, and its properties are evaluated by computer simulations at the gate level using 0.18-µm CMOS standard cell array technology. As a result, the power consumption of the proposed DMF is estimated to be 9.3 mW (@15.6 MHz, 1.6 V), which is below 40% of the power consumed by a general DMF.
ER -