A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division

Hideki YAMAUCHI; Shigeyuki OKADA; Kazuhiko TAKETA; Tatsushi OHYAMA

A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division

Hideki YAMAUCHI, Shigeyuki OKADA, Kazuhiko TAKETA, Tatsushi OHYAMA

Full Text Views

0

Cite this

Summary :

A VLSI-specific wavelet processing technique has been developed and implemented as a processor in accordance with the JPEG2000 specification. This proposed procedure of discrete wavelet transforms uses an altered calculation equations and makes use of intermediate results through wavelet calculation. The implementation of the proposed procedure is capable of realizing a highly efficient DWT for large size images in spite of using low hardware costs and a small size buffering memory. In order to obtain fast EBCOT processing, three types of parallel processing are introduced in the EBCOT architecture. The processor performs compression of 720480 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 32 MHz or lower. Furthermore, it need not divide an image into tiles so that the problem of deterioration of image quality due to tile division does not occur. A prototype of this processor has been fabricated in a 0.25-µm 5-layer CMOS process. The chip is 10.210.4 mm² in size and consumes 2.0 W when supplied with 2.5 V and 32 MHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.448-456

Publication Date: 2004/04/01

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)

Category

Cite this

Copy

Hideki YAMAUCHI, Shigeyuki OKADA, Kazuhiko TAKETA, Tatsushi OHYAMA, "A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 4, pp. 448-456, April 2004, doi: .
Abstract: A VLSI-specific wavelet processing technique has been developed and implemented as a processor in accordance with the JPEG2000 specification. This proposed procedure of discrete wavelet transforms uses an altered calculation equations and makes use of intermediate results through wavelet calculation. The implementation of the proposed procedure is capable of realizing a highly efficient DWT for large size images in spite of using low hardware costs and a small size buffering memory. In order to obtain fast EBCOT processing, three types of parallel processing are introduced in the EBCOT architecture. The processor performs compression of 720480 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 32 MHz or lower. Furthermore, it need not divide an image into tiles so that the problem of deterioration of image quality due to tile division does not occur. A prototype of this processor has been fabricated in a 0.25-µm 5-layer CMOS process. The chip is 10.210.4 mm² in size and consumes 2.0 W when supplied with 2.5 V and 32 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_4_448/_p

Copy

@ARTICLE{e87-c_4_448,
author={Hideki YAMAUCHI, Shigeyuki OKADA, Kazuhiko TAKETA, Tatsushi OHYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division},
year={2004},
volume={E87-C},
number={4},
pages={448-456},
abstract={A VLSI-specific wavelet processing technique has been developed and implemented as a processor in accordance with the JPEG2000 specification. This proposed procedure of discrete wavelet transforms uses an altered calculation equations and makes use of intermediate results through wavelet calculation. The implementation of the proposed procedure is capable of realizing a highly efficient DWT for large size images in spite of using low hardware costs and a small size buffering memory. In order to obtain fast EBCOT processing, three types of parallel processing are introduced in the EBCOT architecture. The processor performs compression of 720480 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 32 MHz or lower. Furthermore, it need not divide an image into tiles so that the problem of deterioration of image quality due to tile division does not occur. A prototype of this processor has been fabricated in a 0.25-µm 5-layer CMOS process. The chip is 10.210.4 mm² in size and consumes 2.0 W when supplied with 2.5 V and 32 MHz.},
keywords={},
doi={},
ISSN={},
month={April},}

Copy

TY - JOUR
TI - A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division
T2 - IEICE TRANSACTIONS on Electronics
SP - 448
EP - 456
AU - Hideki YAMAUCHI
AU - Shigeyuki OKADA
AU - Kazuhiko TAKETA
AU - Tatsushi OHYAMA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - A VLSI-specific wavelet processing technique has been developed and implemented as a processor in accordance with the JPEG2000 specification. This proposed procedure of discrete wavelet transforms uses an altered calculation equations and makes use of intermediate results through wavelet calculation. The implementation of the proposed procedure is capable of realizing a highly efficient DWT for large size images in spite of using low hardware costs and a small size buffering memory. In order to obtain fast EBCOT processing, three types of parallel processing are introduced in the EBCOT architecture. The processor performs compression of 720480 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 32 MHz or lower. Furthermore, it need not divide an image into tiles so that the problem of deterioration of image quality due to tile division does not occur. A prototype of this processor has been fabricated in a 0.25-µm 5-layer CMOS process. The chip is 10.210.4 mm² in size and consumes 2.0 W when supplied with 2.5 V and 32 MHz.
ER -