IEICE TRANSACTIONS on Electronics
High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor
Summary :
This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E105-C No.7 pp.316-323
- Publication Date
- 2022/07/01
- Publicized
- 2022/01/14
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2021CDP0001
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Fukashi MORISHITA
Renesas Electronics Corporation
Wataru SAITO
Renesas Electronics Corporation
Norihito KATO
Renesas Electronics Corporation
Yoichi IIZUKA
Renesas Electronics Corporation
Masao ITO
Renesas Electronics Corporation
Keyword
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Fukashi MORISHITA, Wataru SAITO, Norihito KATO, Yoichi IIZUKA, Masao ITO, "High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor" in IEICE TRANSACTIONS on Electronics,
vol. E105-C, no. 7, pp. 316-323, July 2022, doi: 10.1587/transele.2021CDP0001.
Abstract: This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021CDP0001/_p
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@ARTICLE{e105-c_7_316,
author={Fukashi MORISHITA, Wataru SAITO, Norihito KATO, Yoichi IIZUKA, Masao ITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor},
year={2022},
volume={E105-C},
number={7},
pages={316-323},
abstract={This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.},
keywords={},
doi={10.1587/transele.2021CDP0001},
ISSN={1745-1353},
month={July},}
Copy
TY - JOUR
TI - High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor
T2 - IEICE TRANSACTIONS on Electronics
SP - 316
EP - 323
AU - Fukashi MORISHITA
AU - Wataru SAITO
AU - Norihito KATO
AU - Yoichi IIZUKA
AU - Masao ITO
PY - 2022
DO - 10.1587/transele.2021CDP0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2022
AB - This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.
ER -
English
