Time-of-flight (TOF) range imaging is a promising technology for various applications such as touchless control, augmented reality interface, and automotive. The TOF range imagers are classified into two methods: direct TOF with single photo avalanche diodes and indirect TOF with lock-in pixels. The indirect TOF range imagers have advantages in terms of a high spatial resolution and high depth precision because their pixels are simple and can handle many photons at one time. This paper reviews and discusses principal lock-in pixels reported both in the past and present, including circuit-based and charge-modulator-based lock-in pixels. In addition, key technologies that include enhancing sensitivity and background suppression techniques are also discussed.

This paper proposes novel test techniques for high accuracy measurement of ADCs and a ramp generator on a CMOS image sensor (CIS) chip. The test circuit for the ADCs has a dual path and has an ability of multi-functional fine pattern generator that can define any input for each column to evaluate CIS specific characteristics electrically. The test circuit for the ramp generator can realize an on-chip current cell test and reject the current cell failure within 1LSB accuracy. We fabricated the test sensor using 55nm CIS process and measured the IP characteristics. Measured results show INL of 14.6LSB, crosstalk of 14.9LSB and column interference noise of 5.4LSB. These measured results agree with the designed values. By using this technique, we confirmed the accurate ADC measurement can be realized without being affected by the ambiguity of the optical input.

The resistor variation can severely affect current reference sources, which may vary up to ±40% in scaled CMOS processes. In addition, such variations make the opamp design challenging and increase the design margin, impacting power consumption. This paper proposes a Time-Based Current Source (TBCS): a robust and process-scalable reference current source suitable for switched-capacitor (SC) circuits. We construct a delay-locked-loop (DLL) to lock the current-starved inverter with the reference clock, enabling the use of the settled current directly as a reference current. Since the load capacitors determine the delay, the generated current is decoupled from resistor values and enables a robust reference current source. The prototype TBCS fabricated in 28nm CMOS achieved a minimal area of 1200um². The current variation is suppressed to half compared to BGR based current sources, confirmed in extensive PVT variation simulations. Moreover, when used as the opamp's bias, TBCS achieves comparable opamp GBW to an ideal current source.

This paper presents a fully integrated yet compact receiver front-end for Sub-GHz applications such as Internet-of-Things (IoT). The low noise amplifier (LNA) matching network leverages an inductance boosting technique. A relatively small on-chip inductor with a compact area achieves impedance matching in such a low frequency. Moreover, a passive-mixer-first mode bypasses the LNA to extend the receiver dynamic-range. The passive mixer provides matching to the 50Ω antenna interface to eliminate the need for additional passive components. Therefore, the receiver can be fully-integrated without any off-chip matching components. The flipped-voltage-follower (FVF) cell is adopted in the low pass filter (LPF) and the variable gain amplifier (VGA) for its high linearity and low power consumption. Fabricated in 65nm LP CMOS process, the proposed receiver front-end occupies 0.37mm² core area, with a tolerable input power ranging from -91.5dBm to -1dBm for 500kbps GMSK signal at 924MHz frequency. The power consumption is 1mW power under a 1.2V supply.

This brief proposes a solar-cell-assisted wireless biosensing system that operates using a biofuel cell (BFC). To facilitate BFC area reduction for the use of this system in area-constrained continuous glucose monitoring contact lenses, an energy harvester combined with an on-chip solar cell is introduced as a dedicated power source for the transmitter. A dual-oscillator-based supply voltage monitor is employed to convert the BFC output into digital codes. From measurements of the test chip fabricated in 65-nm CMOS technology, the proposed system can achieve 99% BFC area reduction.

This paper proposes a novel multi-layer substrate integrated waveguide (SIW) resonator loaded with asymmetric E-shaped slot-lines and shows a tri-band band-pass filter (BPF) using the proposed structure. In the previous literature, various SIW resonators have been proposed to simultaneously solve the problems of large area and high insertion loss. Although these SIWs have a lower insertion loss than planar-type resonators using a printed circuit board, the size of these structures tends to be larger. A multi-layer SIW resonator loaded with asymmetric E-shaped slot-lines can solve the above problems and realize a tri-band BPF without increasing the size to realize further miniaturization. The theoretical design method and the structural design are shown. Moreover, the configured structure is fabricated and measured for showing the validity of the design method in this paper.