IEICE TRANSACTIONS on Electronics
A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications
Summary :
Multiport SRAMs are frequently installed in network and/or telecommunication VLSIs to implement smart functions. This paper presents a high speed and low-power dual-port (i.e., 1W+1R two-port) SRAM macro customized for serial access operations. To reduce the wasted power dissipation due to subthreshold leakage currents, the supply voltage for 10T memory cells is lowered to 1 V and a power switch is prepared for every 64 word drivers. The switch is activated with look-ahead decoder-segment activation logic, so there is no penalty when selecting a wordline. The data I/O circuitry with a new column-based configuration makes it possible to hide the bitline precharge operation with the sensing operation in the read cycle ahead of it; that is, we have successfully reduced the read latency by a half clock cycle, resulting in a pure two-stage pipeline. The SRAM macro installed in a 4K-entry × 33-bit FIFO memory, fabricated with a 0.3-µm fully-depleted-SOI CMOS process, achieved a 500-MHz operation in the typical conditions of 2- and 1-V power supplies, and 25°C. The power consumption during the standby time was less than 1.0 mW, and that at a practical operating frequency of 400 MHz was in a range of 47-57 mW, depending on the bit-stream data pattern.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E100-C No.11 pp.1061-1068
- Publication Date
- 2017/11/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E100.C.1061
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Nobutaro SHIBATA
NTT Microsystem Integration Laboratories
Mayumi WATANABE
NTT Microsystem Integration Laboratories
Takako ISHIHARA
NTT Microsystem Integration Laboratories
Keyword
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Nobutaro SHIBATA, Mayumi WATANABE, Takako ISHIHARA, "A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications" in IEICE TRANSACTIONS on Electronics,
vol. E100-C, no. 11, pp. 1061-1068, November 2017, doi: 10.1587/transele.E100.C.1061.
Abstract: Multiport SRAMs are frequently installed in network and/or telecommunication VLSIs to implement smart functions. This paper presents a high speed and low-power dual-port (i.e., 1W+1R two-port) SRAM macro customized for serial access operations. To reduce the wasted power dissipation due to subthreshold leakage currents, the supply voltage for 10T memory cells is lowered to 1 V and a power switch is prepared for every 64 word drivers. The switch is activated with look-ahead decoder-segment activation logic, so there is no penalty when selecting a wordline. The data I/O circuitry with a new column-based configuration makes it possible to hide the bitline precharge operation with the sensing operation in the read cycle ahead of it; that is, we have successfully reduced the read latency by a half clock cycle, resulting in a pure two-stage pipeline. The SRAM macro installed in a 4K-entry × 33-bit FIFO memory, fabricated with a 0.3-µm fully-depleted-SOI CMOS process, achieved a 500-MHz operation in the typical conditions of 2- and 1-V power supplies, and 25°C. The power consumption during the standby time was less than 1.0 mW, and that at a practical operating frequency of 400 MHz was in a range of 47-57 mW, depending on the bit-stream data pattern.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E100.C.1061/_p
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@ARTICLE{e100-c_11_1061,
author={Nobutaro SHIBATA, Mayumi WATANABE, Takako ISHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications},
year={2017},
volume={E100-C},
number={11},
pages={1061-1068},
abstract={Multiport SRAMs are frequently installed in network and/or telecommunication VLSIs to implement smart functions. This paper presents a high speed and low-power dual-port (i.e., 1W+1R two-port) SRAM macro customized for serial access operations. To reduce the wasted power dissipation due to subthreshold leakage currents, the supply voltage for 10T memory cells is lowered to 1 V and a power switch is prepared for every 64 word drivers. The switch is activated with look-ahead decoder-segment activation logic, so there is no penalty when selecting a wordline. The data I/O circuitry with a new column-based configuration makes it possible to hide the bitline precharge operation with the sensing operation in the read cycle ahead of it; that is, we have successfully reduced the read latency by a half clock cycle, resulting in a pure two-stage pipeline. The SRAM macro installed in a 4K-entry × 33-bit FIFO memory, fabricated with a 0.3-µm fully-depleted-SOI CMOS process, achieved a 500-MHz operation in the typical conditions of 2- and 1-V power supplies, and 25°C. The power consumption during the standby time was less than 1.0 mW, and that at a practical operating frequency of 400 MHz was in a range of 47-57 mW, depending on the bit-stream data pattern.},
keywords={},
doi={10.1587/transele.E100.C.1061},
ISSN={1745-1353},
month={November},}
Copy
TY - JOUR
TI - A SOI Multi-VDD Dual-Port SRAM Macro for Serial Access Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 1061
EP - 1068
AU - Nobutaro SHIBATA
AU - Mayumi WATANABE
AU - Takako ISHIHARA
PY - 2017
DO - 10.1587/transele.E100.C.1061
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E100-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2017
AB - Multiport SRAMs are frequently installed in network and/or telecommunication VLSIs to implement smart functions. This paper presents a high speed and low-power dual-port (i.e., 1W+1R two-port) SRAM macro customized for serial access operations. To reduce the wasted power dissipation due to subthreshold leakage currents, the supply voltage for 10T memory cells is lowered to 1 V and a power switch is prepared for every 64 word drivers. The switch is activated with look-ahead decoder-segment activation logic, so there is no penalty when selecting a wordline. The data I/O circuitry with a new column-based configuration makes it possible to hide the bitline precharge operation with the sensing operation in the read cycle ahead of it; that is, we have successfully reduced the read latency by a half clock cycle, resulting in a pure two-stage pipeline. The SRAM macro installed in a 4K-entry × 33-bit FIFO memory, fabricated with a 0.3-µm fully-depleted-SOI CMOS process, achieved a 500-MHz operation in the typical conditions of 2- and 1-V power supplies, and 25°C. The power consumption during the standby time was less than 1.0 mW, and that at a practical operating frequency of 400 MHz was in a range of 47-57 mW, depending on the bit-stream data pattern.
ER -
English
