IEICE TRANSACTIONS on Electronics
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Summary :
This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.10 pp.1669-1679
- Publication Date
- 2011/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.1669
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Shota ISHIHARA, Ryoto TSUCHIYA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, "Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 10, pp. 1669-1679, October 2011, doi: 10.1587/transele.E94.C.1669.
Abstract: This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1669/_p
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@ARTICLE{e94-c_10_1669,
author={Shota ISHIHARA, Ryoto TSUCHIYA, Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture},
year={2011},
volume={E94-C},
number={10},
pages={1669-1679},
abstract={This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.},
keywords={},
doi={10.1587/transele.E94.C.1669},
ISSN={1745-1353},
month={October},}
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TY - JOUR
TI - Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1669
EP - 1679
AU - Shota ISHIHARA
AU - Ryoto TSUCHIYA
AU - Yoshiya KOMATSU
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2011
DO - 10.1587/transele.E94.C.1669
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2011
AB - This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.
ER -
English
