An on-chip temperature compensation active bias circuit having tunable temperature slope has been proposed, and its application to an X-band GaAs FET monolithic microwave integrated circuit (MMIC) power amplifier (PA) is described. The proposed bias circuit can adjust the temperature slope of gate voltage according to the bias condition of the PA, and also realizes the higher temperature slope of the gate voltage by employing the diode and the FET which operates at near threshold voltage (V_t) in the bias circuit. As a result, the gain of PAs operated at any bias conditions is kept almost constant against temperature by applying the proposed bias circuit. Moreover, the proposed bias circuit can be integrated in the same chip with the MMIC PA since it does not need off-chip components, and operates with only negative voltage source. The fabricated results of the on-chip temperature compensation active bias circuit shows that the temperature slope of the gate voltage varies from 2.1 to 6.3 mV/, which is enough to compensate the gain of not only class-B PA but also class-A PA. The gain deviation of the developed GaAs FET MMIC PA with the proposed bias circuit has been reduced from 3.3 dB to 0.6 dB in the temperature range of 100.

A fully differential high gain V-band three-stage transformer-coupled power amplifier (PA) is designed and implemented in 65 nm CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanism, single-ended to differential conversion, and input/inter-stage/output matching are used to facilitate a compact amplifier design. The design and optimization methodologies of active and passive devices are presented. With a cascode configuration, the amplifier achieves a linear gain of 30.5 dB centered at 63.5 GHz and a -40 dB reverse isolation under a 1 V supply, which compares favorably to recent published V-band PAs. The amplifier delivers 9 dBm and 13 dBm saturation output power (P_sat) under 1 V and 1.5 V supplies, respectively, and occupies a core chip area of 0.05 mm². The measurement results validate a high gain and area-efficient power amplifier design methodology in deep-scaled CMOS for applications in millimeter-wave communication.

To reduce laborious tasks of the phase determination, our previous paper has proposed a method to derive phase reference for two-tone intermodulation distortion (IMD) measurement of a power amplifier (PA) by using small-signal S-parameters. Since the method is applicable to low output power level, this paper proposes an iterative process to extend the applicable power level up to 1-dB compression. The iterative process is based on extraction of linear response: the principle of the extraction is described theoretically by using an accurate model of the PA with memory effect. Measurement of two-tone IMD is made for a GaN FET PA. Validity of the iteration is confirmed as convergence of the extracted linear response to that given by the product of S₂₁ and input signal. Measured results also show validity of the physical model of the memory effect provided by Vuolevi et al. because beat frequency dependences of IMD's are accurately fitted by bias impedances at even order harmonics of envelope frequency. The PA is characterized by using measured results and the third and fifth order inverses of the PA are designed. Improvement of IMD is theoretically confirmed by using the inverses as predistorters.

This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18 µm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise of -125.8 dBc/Hz at 4 MHz offset from the carrier frequency of 3.4 GHz. It exhibits a frequency tuning range from 1.23 GHz to 4.17 GHz with coarse and fine frequency tuning sensitivity of 1.08 MHz/mV and 120 kHz/mV, respectively.

High-power T/R switch with GaN HEMT technology is successfully developed, and the design theory is formulated. The proposed switch employs an asymmetric series-shunt/shunt configuration. Because the power handling capability of the proposed switch is mainly dependent of the breakdown voltage of FETs, the proposed circuit can make full use of the characteristics of the GaN HEMT technology. The switch has a high degree of freedom for the FET gate widths, so the low insertion loss can be obtained while keeping high-power performances. To verify this methodology, T/R switch has been fabricated in X-band. The fabricated switch has demonstrated an insertion loss of 1.8 dB in Rx-mode, 1.2 dB in Tx-mode and power handling capability of 20 W in 53% bandwidth.

We propose two types of active directional couplers to assure high TX cancellation: an asymmetric type and a symmetric type. For attaining low receiving through loss, coupling capacitors used in conventional couplers are replaced by amplifiers in the proposed active directional couplers. The asymmetric active directional coupler is composed of a small number of components and simple structure. The symmetric active directional coupler has wide-bandwidth TX cancellation. Measurement results show that receiving through loss of -5.3 dB and the TX cancellation of -67.6 dB are obtained in the asymmetric active directional coupler, and receiving through loss of -6.7 dB and the TX cancellation of -66.4 dB are obtained in the symmetric active directional coupler. Compared to the asymmetric active directional coupler, the symmetric active directional coupler has advantage of wider bandwidth of 1.25 MHz to reduce TX leakage of less than -55 dB. Both the proposed active directional couplers achieve high TX cancellation, and the symmetric active directional coupler can be applied in a UHF RFID system with 10-m communication range.

We present a highly integrated quasi-millimeter-wave receiver MMIC that integrates 22 circuits in a 3 2.3 mm area using three-dimensional MMIC (3D-MMIC) technology. The MMIC achieves low noise (3 dB) and high gain (41 dB) at 26 GHz by using an on-chip image reject filter. It integrates a multiply-by-eight (X8) local oscillator (LO) chain with the IF frequency of the 2.4 GHz band and can use low-cost voltage-controlled oscillators (VCOs) and demodulators in a 2–3 GHz frequency band. Multilayer inductors contribute to the miniaturization especially in a 2–12 GHz frequency band. Furthermore, it achieves a high dynamic range by using two step attenuators with a new built-in inverter using an N-channel depression field-effect transistor (FET). The power consumption of the MMIC is only 450 mW.

This paper presents the analytical results of the effects of jitter and intersymbol interference (ISI) on a millimeter-wave impulse radio (IR) transceiver, compared with the performance of a developed 10-Gb/s W-band IR-transmitter prototype. The IR transmitter, which is compact and cost-effective, consists of a pulse generator (PG) that creates an extremely short pulse, a band-pass filter (BPF) that shapes the short pulse to the desired millimeter-wave pulse (wavelet), and an optional power amplifier. The jitters of the PG and ISI from the BPF are a hindrance in making the IR transceiver robust and in obtaining excellent performance. One analysis verified that, because of a novel retiming architecture, the random jitter and the data-dependent jitter from the PG give only a small penalty of < 0.5-dB increase in the signal-to-noise ratio (SNR) for achieving a bit error rate (BER) of < 10^-12. An alternative analysis on the effect of ISI from the BPF indicated that using a Gaussian BPF enables a transmission with a BER of < 10^-12 up to a data rate of 1.4 times as large as the bandwidth of the BPF, which is twice as high as that of a conventional amplitude shift keying (ASK) system. The analysis also showed that the IR system is more sensitive to the ISI than the ASK system and suggested that the mismatching of the skirt characteristics of the developed BPF with those of a Gaussian BPF causes tail lobes following the wavelet, resulting in an on/off ratio of 15 dB and hence, an SNR penalty of 6 dB.

This paper investigates characteristics of periodic structure of ferrite and dielectric slabs in cutoff waveguide which include left-handed operation. Transmission line model and finite element simulation are used to get dispersion characteristics and scattering parameters. Band pass response of left-handed ferrite mode at negative permeability region are discussed with backward wave phenomenon. Theoretical results show that by choosing appropriate ratio of (1) ferrite width and dielectric width, and (2) ferrite length and dielectric length, band pass response with steep edge characteristics can be obtained by the LH ferrite mode, which are confirmed with experiments using single crystal of yttrium iron garnet ferrite. Good band pass and phase shift responses are observed in S band.

This paper proposes a novel waveguide intersection separating two H-plane waveguide systems from each other. If a four-port network in a four-fold rotational symmetry is completely matched, it has necessarily intersection properties. The proposed waveguide intersection consists of a square H-plane waveguide planar circuit connected four input/output waveguide ports in a four-fold rotational symmetry, and several metallic posts inserted at the junction without destroying the symmetry to realize a perfect matching. By optimizing the circuit parameters, high isolation properties are obtained in a relatively wide frequency band of about 8.6% for return loss and isolation better than 20 and 30 dB, respectively, for a circuit designed at 10 GHz. The proposed waveguide intersection can be analyzed by H-plane planar circuit approach, and possess advantages of compactness, simplicity, and high-power handling capability. Furthermore, an SIW intersection is designed by applying H-plane planar circuit approach to a waveguide circuit filled with dielectric material, and high isolation properties similar to H-plane waveguide intersection can be realized. The validity of these design concepts is confirmed by em-simulations and experiments.

A matched load for post-wall waveguide (SIW; Substrate Integrated Waveguide) is presented. It consists of an electrically-shorted post-wall waveguide and a rectangular thin-film resistor sheet on the surface of the waveguide, resulting in a quite compact structure without three-dimensional bulky absorber as in conventional waveguide matched loads. A fabricated X-band matched load has achieved less than -20 dB reflection in more than 20% relative bandwidth.

In this paper, we propose a novel feeding structure for a coaxial-excited compact waveguide filter, which is composed of planar resonators called frequency-selective surfaces (FSSs). In our proposed feeding structure, new FSSs located at the input and output ports are directly excited by the coaxial line. By using the FSSs, the transition from the TEM mode to the TE₁₀ mode is realized by the resonance of the FSSs. Therefore, the backshort length from the coaxial probe to the shorted waveguide end can be made much shorter than one-quarter of the guided wavelength. Additionally, the coaxial-excited FSS provides one transmission zero at each stopband. As a design example, a three-stage bandpass filter with 4% bandwidth at the X band is demonstrated. The designed filter has a very compact size of one cavity and has high skirt selectivity with six transmission zeros. The effectiveness of the design is confirmed by the comparison of frequency characteristics obtained by the simulation and measurement.

In this paper, a novel design of planar dual-band multi-way lossless power dividers (PDs), namely Bagley Polygon PDs, is presented. The proposed PDs use Π-type dual-band transformers as basic elements, whose design formulas are analyzed and simplified to a concise form. The equivalent circuit of the dual-band Bagley Polygon PD is established, based on which design equations are derived mathematically. After that, the design procedure is demonstrated, and special cases are discussed. To verify the validity of the proposed design, 3-way and 5-way examples are simulated and fabricated at two IMT-Advanced bands of 1.8 GHz and 3.5 GHz, then simulation and measurement results are provided. The presented PDs have good performances on the bandwidths and phase shifts. Furthermore, the planar configuration leads to convenient design procedure and easy fabrication.

In this paper, a rat-race hybrid coupler based on an open complementary split ring resonator (OCSRR) is presented. By embedding the OCSRR in the microstrip transmission line, slow-wave effect is introduced to achieve size reduction. The proposed rat-race coupler size is 37% smaller than the conventional rat-race coupler. Besides, the proposed coupler provides better third harmonic suppression up to 35 dB. The simulated results are compared with the measured data and good agreement is reported.

In this study, the design and fabrication of a 110–140-GHz varistor mode frequency tripler made with four Schottky diodes pair are presented. Nonlinear simulations were performed to calculate the optimum diode embedding impedance and the required input power. A compact microstrip resonant cell (CMRC) filter was introduced for the first time in submillimeter multiplier, instead of the traditional low-and-high impedance microstrip filter. The shorter size and the wider stop band of the CMRC filter improved the performance of the tripler. The tripler exhibited the best conversion efficiency of 5.2% at 129 GHz and peak output power of 5.3 mW at 125 GHz. Furthermore, within the output bandwidth from 110 to 140 GHz, the conversion efficiency was greater than 1.5%.

On the huge-scale array antenna for SSPS (space solar power systems), the problem of faulty elements and effect of mutual coupling between array elements should be considered in practice. In this paper, the effect of faulty elements as well as mutual coupling on the performance of the huge-scale array antenna are analyzed by using the proposed IEM/LAC. The result shows that effect of faulty elements and mutual coupling on the actual gain of the huge-scale array antenna are significant.

A circularly-polarized planar array antenna using hexagonal aperture elements is proposed. A 22-element subarray as the basic unit is excited by a corporate-feed circuit located in the lower layer of the double-layered antenna. The hexagonal aperture is designed to achieve a good axial ratio in the boresight. A 1616-element array antenna with uniform element spacing smaller than the free-space wavelength was fabricated by diffusion bonding of laminated thin metal plates for the 60 GHz-band. The high gain of 33.4 dBic is measured with 91.6% antenna efficiency, including losses.

This paper presents a 100–120-GHz pulse transmitter chip with a 5424 on-chip loop antenna array for the purpose of beam-formability in portable millimeter-wave (mm-wave) active imaging applications. We present a new idea for silicon-based mm-wave pulse beam-forming by using voltage-varied CMOS inverter chain. This 4-mm4-mm transmitter chip is designed and fabricated in a 2.5-V 0.25-µm 4-metal-layer Si-Ge Bi-CMOS process. The 30-µm30-µm loop antenna located on the top-metal layer operates as an coil in an integrated mm-wave pulse generator. Each of on-chip pulse generators employing under-damped/over-damped conditions to produce mm-wave pulses includes an R-L-C circuit, a bipolar junction transistor (BJT) operated as a switch and a CMOS inverter chain circuit for shaping the rising edge of the input clock. Simulation results by ADS 2009 and HSPICE show that loop antenna' inductance and resistance at 80–120-GHz are 51 pH and 3 Ω, respectively. A simulation performance of an integrated 136 loop antenna array illustrates the variation of maximum radiation angles depending on different phase values between array's elements. By using an mm-wave power meter, a 90–140-GHz standard horn antenna and a Schottky diode detector, several measured radiation patterns of this loop antenna array chip are achieved. From the measurement result, we demonstrate the possibility of an integrated mm-wave pulse generator for the purpose of beam-forming by changing power supplies of inverter chains.

Microwave/millimeter-wave phase and amplitude characteristics of the optically controlled phased array antenna with a different SMF for each antenna feed were measured. Suitable phases for the beam steering can be realized by the adjustment of the LD wavelength independently with multiple SMFs. In addition to the phase, amplitude of each antenna feed can be controlled stably using LD current without phase variation. Furthermore, effectiveness of the calibration method of the phased array using multiple SMFs by LD wavelength adjustment is experimentally verified. Excellent microwave/millimeter-wave phase characteristics using 2- and 3-element optically controlled phased array feed were experimentally demonstrated with calibration of the phases. Phase characteristics of the array using multiple SMFs were also compared with that using a single SMF experimentally.

Accurate device models are very important for the design of high-frequency circuits. One of the factors degrading the accuracy of device models appears during the de-embedding procedure. Generally, to obtain device characteristics without parasitic elements such as pads, a de-embedding procedure is essential. However, some errors are introduced during this procedure, which degrades the accuracy of device models. In this paper, we demonstrate that such errors due to de-embedding are cancelled in cascade circuit design, meaning that cascade circuits can be designed without knowing the actual characteristics of devices. Because it is difficult to know the actual characteristics of devices at a high frequency, the cancellation of the de-embedding error is expected to improve the accuracy of device models at high frequencies. After giving a theoretical treatment of de-embedding error cancellation, we report the results of simulations and measurements performed for verification.

A 100 GHz grooved circular empty cavity is proposed for the low loss dielectric substrate measurements by the cut-off circular waveguide method in W band. The influence of the excitation holes for the coaxial cable with a small loop are revealed by an FEM based 3D electromagnetic simulator. And also, the diameter of the excitation hole is determined based on the calculated results and the manufacturing accuracy. Then, two kinds of four 100 GHz grooved circular empty cavities are fabricated. Comparative experiments of the cavities with the different excitation holes validate the simulated results. Moreover, the complex permittivity of a PTFE plate is measured using the fabricated four cavities by the cut-off circular waveguide method around 84 GHz. The measured results agree within measurement error about 0.5% for ε_r and 5% for tanδ. Also, these results accord with results measured by the Whispering-Gallery mode resonator method in 85–110 GHz band. It verifies that the proposed 100 GHz cavity for the cut-off waveguide method is useful for the complex permittivity measurement of low loss dielectric substrates in W band.

In this paper, we show that the covariance-eigenvalue approach converges much faster than using cumulative distribution function (CDF) for determining diversity gain from channel measurements in reverberation chamber. The covariance-eigenvalue approach can be used for arbitrary multi-port antennas, but it is limited to Maximum Ratio Combining (MRC).

In this study, we demonstrate an acceleration of flexible generalized minimal residual algorithm (FGMRES) implemented with the method of moments and the fast multipole method (FMM), based on a combined tangential formulation. For the implementation of the FGMRES incorporated with the FMM concept, we propose a new definition of the truncation number for the FMM operator within the inner solver. The proposed truncation number provides an optimal variable preconditioner by controlling the accuracy and computational cost of the inner iteration. Moreover, to further accelerate the convergence, we introduce the concept of a multistage preconditioner. Numerical experiments reveal that our new version of FGMRES, based on the proposed truncation number for the inner solver and the multistage preconditioner, achieves outstanding acceleration of the convergence for large-scale and practical electromagnetic scattering and radiation problems with several levels of geometrical complexity.

This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.

A low-power low-noise intermediate-frequency (IF) circuit is proposed for Gaussian frequency shift keying (GFSK) low-IF receivers. The proposed IF circuit is realized by an all-analog architecture composed of a couple of limiting amplifiers (LAs) and received signal strength indicators (RSSIs), a couple of band-pass filters (BPFs), a frequency detector (FD), a low-pass filter (LPF) and a slicer. The LA and RSSI are realized by an optimized combination of folded amplifiers and current subtractor based rectifiers to avoid the process induced depressing on accuracy. In addition, taking into account the nonlinearity and static current of rectifiers, we propose an analytical model as an accurate approximation of RSSIs' transfer character. An active-RC based GFSK demodulation scheme is proposed, and then both low power consumption and a large dynamic range are obtained. The chip is implemented with HJTC 0.18 µm CMOS technology and measured under an intermediate frequency of 200 kHz, a data rate of 100 kb/s and a modulation index of 1. The RSSI has a dynamic range of 51 dB with a logarithmic linearity error of less than 1 dB, and the slope is 23.9 mV/dB. For 0.1% bit error ratio (BER), the proposed IF circuit has the minimum input signal-to-noise ratio (SNR) of 5 dB and an input dynamic range of 55.4 dB, whereas it can tolerate a frequency offset of -3%+9.5% at 6 dB input SNR. The total power consumption is 5.655.89 mW.

A reliable antifuse scheme has been very hard to build, which has precluded its implementation in DRAM products. We devised a very reliable multi-cell structure to cope with the large process variation in the DRAM-cell-capacitor type antifuse system. The programming current did not rise above 564 µA even in the nine-cell case. The cumulative distribution of the successful rupture in the multi-cell structure could be curtailed dramatically to less than 15% of the single-cell's case and the recovery problem of programmed cells after the thermal stress (300) had disappeared. In addition, we also presented a Post-Package Repair (PPR) scheme that could be directly coupled to the external high-voltage power rail via an additional pin with small protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1 Gbit DDR SDRAM was fabricated using Samsung's advanced 50 nm DRAM technology, successfully proving the feasibility of the proposed antifuse system implemented in it.

In this paper, a highly linear and low noise CMOS active RF tracking filter for a digital TV tuner is presented. The G_m cell of the G_m-C filter is based on a dynamic source degenerated differential pair with an optimized transistor size ratio, thereby providing good linearity and high-frequency operation. The proposed RF tracking filter architecture includes two complementary parallel paths, which provide harmonic rejection in the low band and unwanted signal rejection in the high band. The fabricated tracking filter based on a 0.13 µm CMOS process shows a 48860 MHz tracking range with 30–32 dB 3rd order harmonic rejection, a minimum input referred noise density of 2.4 nV/, and a maximum IIP3 of 0 dBm at 3 dB gain while drawing 39 mA from a 1.2-V supply. The total chip area is 1 mm0.9 mm.

To reduce power consumption of wireless terminals, we have developed ultra-low leakage regulator circuits that control the intermittent terminal operation with very small activity ratio. The regulator circuits supply about 100 mA in the active mode and cut the leakage current to a nanoampere level in the standby mode. The operation of the ultralow-leakage regulator circuits with CMOS/SOI and bulk technologies is described. The leakage-current reduction mechanism in a proposed power switch with bulk technology is explained. Measurement shows that the power switch using reversely biased bulk transistors has a leakage current that is almost as small as that of conventional CMOS/SOI transistor switches.

A MB-OFDM UWB transmitter with on-chip transformer and LO leakage calibration for WiMedia bandgroup 1 is presented. The measurements show a gain-flatness of 1 dB, an LOLRR of -53 dBc/-43 dBc (wi/o cali), an EVM of 2.2% with a power consumption of 22 mW and an area of 1.26 mm².