A 100 GHz grooved circular empty cavity is proposed for the low loss dielectric substrate measurements by the cut-off circular waveguide method in W band. The influence of the excitation holes for the coaxial cable with a small loop are revealed by an FEM based 3D electromagnetic simulator. And also, the diameter of the excitation hole is determined based on the calculated results and the manufacturing accuracy. Then, two kinds of four 100 GHz grooved circular empty cavities are fabricated. Comparative experiments of the cavities with the different excitation holes validate the simulated results. Moreover, the complex permittivity of a PTFE plate is measured using the fabricated four cavities by the cut-off circular waveguide method around 84 GHz. The measured results agree within measurement error about 0.5% for εr and 5% for tanδ. Also, these results accord with results measured by the Whispering-Gallery mode resonator method in 85–110 GHz band. It verifies that the proposed 100 GHz cavity for the cut-off waveguide method is useful for the complex permittivity measurement of low loss dielectric substrates in W band.

Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.

In an IoT system, neural networks have the potential to perform advanced information processing in various environments. To clarify this, the robustness of a restricted Boltzmann machine (RBM) used for deep neural networks, such as a deep belief network (DBN), was studied in this paper. Even if memory or logic errors occurred in the circuit operating in the RBM while pre-training the DBN, they did not affect the identification rate of the DBN, showing the robustness of the RBM. In addition, robustness against soft errors was evaluated. The soft errors had almost no influence on the RBM unless they were as large as 1012 times or more in the 50-nm CMOS process.

We propose a Simulink model of a ring oscillator using saturating integrators. The oscillator's period is tuned via the saturation time of the integrators. Thus, timing jitters due to white and flicker noises are easily introduced into the model, enabling an efficient phase noise evaluation before transistor-level circuit design.

We have investigated the relationship between particle removal efficiency and etched depth in SC-1 solution (the mixture composed of ammonium hydroxide, hydrogen peroxide and DI water) for Si wafers. The Si etching rate increases with increasing NH4OH (ammonium hydroxide) concentration. The particle removal efficiency depends on the etched Si depth, and is independent of NH4OH concentration. The minimum required Si etching depth to get over 95% particle removal efficiency is 4 nm. Particles on the Si wafers exponentially decrease with increasing the etched Si depth. However the particle removal efficiency is not affected by particle size ranging from 0.2 to 0.5 µm. The particle removal mechanism on the Si wafers in SC-1 solution is dominated by the lift-off of particles due to Si undercutting and redeposition of the removed particle.

A vibration-to-electric energy converter as a power generator through a variable-resonating capacitor is theoretically and experimentally demonstrated as a potential on-chip battery. The converter is constructed from three components: a mechanical-variable capacitor, a charge-transporter circuit and a timing-capture control circuit. An optimum design methodology is theoretically described to maximize the efficiency of the vibration-to-electric energy conversion. The energy-conversion efficiency is analyzed based on the following three factors: the mechanical-energy to electric-energy conversion loss, the parasitic elements loss in the charge-transporter circuit and the timing error in the timing-capture circuit. Through the mechanical-energy conversion analysis, the optimum condition for the resonance is found. The parasitic elements in the charge-transporter circuit and the timing management of the capture circuit dominate the output energy efficiency. These analyses enable the optimum design of the energy-conversion system. The converter is fabricated experimentally. The practical measured power is 0.12 µW, and the conversion efficiency is 21%. This efficiency is calculated from a 43% mechanical-energy conversion loss and a 63% charge-transportation loss. The timing-capture circuit is manually controlled in this experiment, so that the timing error is not considered in the efficiency. From our result, a new system LSI application with an embedded power source can be explored for the ubiquitous computing world.

A charge-integration read scheme has been developed for a solid-nanopore DNA-sequencer that determines a genome by direct and electrical measurements of transverse tunneling current in single-stranded DNA. The magnitude of the current was simulated with a first-principles molecular dynamics method. It was found that the magnitude is as small as in the sub-pico ampere range, and signals from four bases represent wide distributions with overlaps between each base. The distribution is believed to originate with translational and rotational motion of DNA in a nanopore with a frequency of over 105 Hz. A sequence scheme is presented to distinguish the distributed signals. The scheme makes widely distributed signals time-integrated convergent by cumulating charge at the capacitance of a nanopore device and read circuits. We estimated that an integration time of 1.4 ms is sufficient to obtain a signal difference of over 10 mV for distinguishing between each DNA base. Moreover, the time is shortened if paired bases, such as A-T and C-G in double-stranded DNA, can be measured simultaneously with two nanopores. Circuit simulations, which included the capacitance of a nanopore calculated with a device simulator, successfully distinguished between DNA bases in less than 2.0 ms. The speed is roughly six orders faster than that of a conventional DNA sequencer. It is possible to determine the human genome in one day if 100-nanopores are operated in parallel.

A 0.3-µm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: 1) a Vcc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability, and layout area; 2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; 3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and 4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed-DRAM's, based on the 4-Mb design.

In this paper, we study a variant of the MINIMUM DOMINATING SET problem. Given an unweighted undirected graph G=(V,E) of n=|V| vertices, the goal of the MINIMUM SINGLE DOMINATING CYCLE problem (MinSDC) is to find a single shortest cycle which dominates all vertices, i.e., a cycle C such that for the set V(C) of vertices in C and the set N(V(C)) of neighbor vertices of C, V(G)=V(C)∪N(V(C)) and |V(C)| is minimum over all dominating cycles in G [6], [17], [24]. In this paper we consider the (in)approximability of MinSDC if input graphs are restricted to some special classes of graphs. We first show that MinSDC is still NP-hard to approximate even when restricted to planar, bipartite, chordal, or r-regular (r≥3). Then, we show the (lnn+1)-approximability and the (1-ε)lnn-inapproximability of MinSDC on split graphs under P≠NP. Furthermore, we explicitly design a linear-time algorithm to solve MinSDC for graphs with bounded treewidth and estimate the hidden constant factor of its running time-bound.

Two types of dynamic termination, latch-type and RC-type, are useful for low-power high-speed chip interconnection where the transmission line is terminated only if the signal is changed. The gate of the termination MOS in the latch-type is driven by a feedback inverter, and that in the RC-type is driven by a differentiating signal through the resistor and capacitor. The power dissipation is 13% for the latch-type, and 11% for the RC-type in a DC termination scheme, and the overshoot is 32% for the latch-type, and 16% for the RC-type in an open scheme, both at a signal amplitude of 2 V. The RC-type is superior for signal swing as low as a 1 V. On the other hand, RC termination requires large capacitance, and thus high power. Diode termination is not effective for a small swing because of the large ON voltage of diodes.

A novel millimeter-wave planar leaky-wave antenna is described which consists of a dielectric slab loaded by metallic periodic strips. Several new techniques are discussed, such as an air-gapped dielectric waveguide to reduce conductor loss of the ground plane, a canceling array to suppress the reflections in the waveguide due to the metallic strips, a compact feed, and a simple polarizer. By applying these new techniques, we achieved an excellent antenna efficiency, exceeding 70% at 76 GHz band for both vertical and 45-degree inclined linear polarizations.

A new error correction block based Hybrid ARQ protocol, in which PHY layer packets are composed of multiple error correction blocks, is devised together with a retransmission control scheme constructed on the basis of these error correction blocks. This protocol is designed dedicatedly for mobile AV stations to provide the high quality digital video transmission through a radio channel. To analyze the performance of this protocol, the frame loss rate vs. the uncorrectable error probability is simulated, in comparison with the ordinary packet based retransmission control. A wireless video transmission system using IEEE802.11b PHY is also described, which has been developed with the use of a Medium Access Control (MAC) LSI to perform the proposed protocol.

A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.

A rectangular waveguide compatible NRD guide E-plane bandpass filter is proposed for 55 GHz band OFDM applications. The NRD guide E-plane bandpass filter is constructed by inserting a metal foil array in the E-plane of NRD guide. Simulation, fabrication, and handling of the filter are not difficult because each resonator is constructed by a couple of metal foils of a simple shape. A Chebyshev response 5-pole bandpass filter with a very narrow bandwidth of 550 MHz is designed and fabricated at 55 GHz band. Simulated and measured filter performances agree well with the design specifications. Insertion loss of the fabricated filter is found to be around 2.0 dB. Although temperature stability of the fabricated filter are found to be within manageable level, the adoption of cyclo olefin polymer can be one of solution for the temperature stability improvement.