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An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic

Yimeng ZHANG, Leona OKAMURA, Tsutomu YOSHIHARA

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Summary :

A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high-speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. PBL belongs to boost logic family, which includes boost logic, enhanced boost logic and subthreshold boost logic. In this paper, PBL has been compared with other charge-recovery logic technologies. To demonstrate the performance of PBL structure, a 4-bit pipeline multiplier is designed and fabricated with 0.18 µm CMOS process technology. The simulation results indicate that the 4-bit multiplier can work at a frequency of 1.8 GHz, while the measurement of test chip is at operation frequency of 161 MHz, and the power dissipation at 161 MHz is 772 µW.

Publication
IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.605-612
Publication Date
2011/04/01
Publicized
Online ISSN
1745-1353
DOI
10.1587/transele.E94.C.605
Type of Manuscript
Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
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