A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core

Osamu NISHII; Yoichi YUYAMA; Masayuki ITO; Yoshikazu KIYOSHIGE; Yusuke NITTA; Makoto ISHIKAWA; Tetsuya YAMADA; Junichi MIYAKOSHI; Yasutaka WADA; Keiji KIMURA; Hironori KASAHARA; Hideo MAEJIMA

doi:10.1587/transele.E94.C.663

IEICE TRANSACTIONS on Electronics

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core

Osamu NISHII, Yoichi YUYAMA, Masayuki ITO, Yoshikazu KIYOSHIGE, Yusuke NITTA, Makoto ISHIKAWA, Tetsuya YAMADA, Junichi MIYAKOSHI, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA, Hideo MAEJIMA

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We built a 12.4 mm12.4 mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-to-seven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4 GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.663-669

Publication Date: 2011/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.663

Type of Manuscript: PAPER

Category: Integrated Electronics

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Osamu NISHII, Yoichi YUYAMA, Masayuki ITO, Yoshikazu KIYOSHIGE, Yusuke NITTA, Makoto ISHIKAWA, Tetsuya YAMADA, Junichi MIYAKOSHI, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA, Hideo MAEJIMA, "A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 4, pp. 663-669, April 2011, doi: 10.1587/transele.E94.C.663.
Abstract: We built a 12.4 mm12.4 mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-to-seven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4 GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.663/_p

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@ARTICLE{e94-c_4_663,
author={Osamu NISHII, Yoichi YUYAMA, Masayuki ITO, Yoshikazu KIYOSHIGE, Yusuke NITTA, Makoto ISHIKAWA, Tetsuya YAMADA, Junichi MIYAKOSHI, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA, Hideo MAEJIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core},
year={2011},
volume={E94-C},
number={4},
pages={663-669},
abstract={We built a 12.4 mm12.4 mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-to-seven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4 GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.},
keywords={},
doi={10.1587/transele.E94.C.663},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core
T2 - IEICE TRANSACTIONS on Electronics
SP - 663
EP - 669
AU - Osamu NISHII
AU - Yoichi YUYAMA
AU - Masayuki ITO
AU - Yoshikazu KIYOSHIGE
AU - Yusuke NITTA
AU - Makoto ISHIKAWA
AU - Tetsuya YAMADA
AU - Junichi MIYAKOSHI
AU - Yasutaka WADA
AU - Keiji KIMURA
AU - Hironori KASAHARA
AU - Hideo MAEJIMA
PY - 2011
DO - 10.1587/transele.E94.C.663
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - We built a 12.4 mm12.4 mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-to-seven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4 GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.
ER -

IEICE TRANSACTIONS on Electronics

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core

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A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core

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