An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference

Indika U. K. BOGODA APPUHAMYLAGE; Shunsuke OKURA; Toru IDO; Kenji TANIGUCHI

doi:10.1587/transele.E94.C.960

An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference

Indika U. K. BOGODA APPUHAMYLAGE, Shunsuke OKURA, Toru IDO, Kenji TANIGUCHI

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This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/ in the temperature range from 0 to 100. The average current consumption is about 8.5 µA in the above temperature range. The core circuit, including current source, opamp, current mirrors and switched capacitor filters, occupies less than 0.0064 mm² (80 µm×80 µm).

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.6 pp.960-967

Publication Date: 2011/06/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.960

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Indika U. K. BOGODA APPUHAMYLAGE, Shunsuke OKURA, Toru IDO, Kenji TANIGUCHI, "An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 6, pp. 960-967, June 2011, doi: 10.1587/transele.E94.C.960.
Abstract: This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/ in the temperature range from 0 to 100. The average current consumption is about 8.5 µA in the above temperature range. The core circuit, including current source, opamp, current mirrors and switched capacitor filters, occupies less than 0.0064 mm² (80 µm×80 µm).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.960/_p

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@ARTICLE{e94-c_6_960,
author={Indika U. K. BOGODA APPUHAMYLAGE, Shunsuke OKURA, Toru IDO, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference},
year={2011},
volume={E94-C},
number={6},
pages={960-967},
abstract={This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/ in the temperature range from 0 to 100. The average current consumption is about 8.5 µA in the above temperature range. The core circuit, including current source, opamp, current mirrors and switched capacitor filters, occupies less than 0.0064 mm² (80 µm×80 µm).},
keywords={},
doi={10.1587/transele.E94.C.960},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference
T2 - IEICE TRANSACTIONS on Electronics
SP - 960
EP - 967
AU - Indika U. K. BOGODA APPUHAMYLAGE
AU - Shunsuke OKURA
AU - Toru IDO
AU - Kenji TANIGUCHI
PY - 2011
DO - 10.1587/transele.E94.C.960
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2011
AB - This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/ in the temperature range from 0 to 100. The average current consumption is about 8.5 µA in the above temperature range. The core circuit, including current source, opamp, current mirrors and switched capacitor filters, occupies less than 0.0064 mm² (80 µm×80 µm).
ER -