IEICE TRANSACTIONS on Electronics
An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference
Summary :
This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.6 pp.960-967
- Publication Date
- 2011/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.960
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Indika U. K. BOGODA APPUHAMYLAGE, Shunsuke OKURA, Toru IDO, Kenji TANIGUCHI, "An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 6, pp. 960-967, June 2011, doi: 10.1587/transele.E94.C.960.
Abstract: This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.960/_p
Copy
@ARTICLE{e94-c_6_960,
author={Indika U. K. BOGODA APPUHAMYLAGE, Shunsuke OKURA, Toru IDO, Kenji TANIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference},
year={2011},
volume={E94-C},
number={6},
pages={960-967},
abstract={This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/
keywords={},
doi={10.1587/transele.E94.C.960},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference
T2 - IEICE TRANSACTIONS on Electronics
SP - 960
EP - 967
AU - Indika U. K. BOGODA APPUHAMYLAGE
AU - Shunsuke OKURA
AU - Toru IDO
AU - Kenji TANIGUCHI
PY - 2011
DO - 10.1587/transele.E94.C.960
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2011
AB - This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/
ER -
English
