Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling

Benjamin DEVLIN; Makoto IKEDA; Kunihiro ASADA

doi:10.1587/transele.E95.C.546

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling

Benjamin DEVLIN, Makoto IKEDA, Kunihiro ASADA

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A 65 nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370 mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6 V, 27 fJ/operation at 264 MHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.546-554

Publication Date: 2012/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E95.C.546

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)

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Benjamin DEVLIN, Makoto IKEDA, Kunihiro ASADA, "Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling" in IEICE TRANSACTIONS on Electronics, vol. E95-C, no. 4, pp. 546-554, April 2012, doi: 10.1587/transele.E95.C.546.
Abstract: A 65 nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370 mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6 V, 27 fJ/operation at 264 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.546/_p

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@ARTICLE{e95-c_4_546,
author={Benjamin DEVLIN, Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling},
year={2012},
volume={E95-C},
number={4},
pages={546-554},
abstract={A 65 nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370 mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6 V, 27 fJ/operation at 264 MHz.},
keywords={},
doi={10.1587/transele.E95.C.546},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling
T2 - IEICE TRANSACTIONS on Electronics
SP - 546
EP - 554
AU - Benjamin DEVLIN
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 2012
DO - 10.1587/transele.E95.C.546
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - A 65 nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370 mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6 V, 27 fJ/operation at 264 MHz.
ER -