IEICE TRANSACTIONS on Electronics
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
Summary :
Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2 V, 65 nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130 MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.643-650
- Publication Date
- 2012/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.643
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
- Category
Authors
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Jinmyoung KIM, Toru NAKURA, Hidehiro TAKATA, Koichiro ISHIBASHI, Makoto IKEDA, Kunihiro ASADA, "On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 4, pp. 643-650, April 2012, doi: 10.1587/transele.E95.C.643.
Abstract: Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2 V, 65 nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130 MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.643/_p
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@ARTICLE{e95-c_4_643,
author={Jinmyoung KIM, Toru NAKURA, Hidehiro TAKATA, Koichiro ISHIBASHI, Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction},
year={2012},
volume={E95-C},
number={4},
pages={643-650},
abstract={Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2 V, 65 nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130 MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.},
keywords={},
doi={10.1587/transele.E95.C.643},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
T2 - IEICE TRANSACTIONS on Electronics
SP - 643
EP - 650
AU - Jinmyoung KIM
AU - Toru NAKURA
AU - Hidehiro TAKATA
AU - Koichiro ISHIBASHI
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 2012
DO - 10.1587/transele.E95.C.643
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2 V, 65 nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130 MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.
ER -
English
