IEICE TRANSACTIONS on Electronics
Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process
Summary :
Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E97-C No.3 pp.188-193
- Publication Date
- 2014/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E97.C.188
- Type of Manuscript
- Special Section PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
- Category
Authors
Xizhu PENG
Yokohama National University
Yuki YAMANASHI
Yokohama National University
Nobuyuki YOSHIKAWA
Yokohama National University
Akira FUJIMAKI
Nagoya University
Naofumi TAKAGI
Kyoto University
Kazuyoshi TAKAGI
Kyoto University
Mutsuo HIDAKA
National Institute of Advanced Industrial Science and Technology (AIST)
Keyword
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Xizhu PENG, Yuki YAMANASHI, Nobuyuki YOSHIKAWA, Akira FUJIMAKI, Naofumi TAKAGI, Kazuyoshi TAKAGI, Mutsuo HIDAKA, "Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process" in IEICE TRANSACTIONS on Electronics,
vol. E97-C, no. 3, pp. 188-193, March 2014, doi: 10.1587/transele.E97.C.188.
Abstract: Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.188/_p
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@ARTICLE{e97-c_3_188,
author={Xizhu PENG, Yuki YAMANASHI, Nobuyuki YOSHIKAWA, Akira FUJIMAKI, Naofumi TAKAGI, Kazuyoshi TAKAGI, Mutsuo HIDAKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process},
year={2014},
volume={E97-C},
number={3},
pages={188-193},
abstract={Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.},
keywords={},
doi={10.1587/transele.E97.C.188},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 188
EP - 193
AU - Xizhu PENG
AU - Yuki YAMANASHI
AU - Nobuyuki YOSHIKAWA
AU - Akira FUJIMAKI
AU - Naofumi TAKAGI
AU - Kazuyoshi TAKAGI
AU - Mutsuo HIDAKA
PY - 2014
DO - 10.1587/transele.E97.C.188
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2014
AB - Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.
ER -
English
