IEICE TRANSACTIONS on Fundamentals
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
Summary :
This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3382-3389
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3382
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Prediction and Analysis
Authors
Keyword
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Takashi SATO, Junji ICHIMIYA, Nobuto ONO, Koutaro HACHIYA, Masanori HASHIMOTO, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3382-3389, December 2005, doi: 10.1093/ietfec/e88-a.12.3382.
Abstract: This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3382/_p
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@ARTICLE{e88-a_12_3382,
author={Takashi SATO, Junji ICHIMIYA, Nobuto ONO, Koutaro HACHIYA, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design},
year={2005},
volume={E88-A},
number={12},
pages={3382-3389},
abstract={This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3382},
ISSN={},
month={December},}
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TY - JOUR
TI - On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3382
EP - 3389
AU - Takashi SATO
AU - Junji ICHIMIYA
AU - Nobuto ONO
AU - Koutaro HACHIYA
AU - Masanori HASHIMOTO
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3382
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.
ER -
English
