IEICE TRANSACTIONS on Fundamentals
Power-Supply Noise Reduction with Design for Manufacturability
Summary :
In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3421-3428
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3421
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Power/Ground Network
Authors
Hiroyuki TSUJIKAWA
Kenji SHIMAZAKI
Shozo HIRANO
Kazuhiro SATO
Masanori HIROFUJI
Junichi SHIMADA
Mitsumi ITO
Kiyohito MUKAI
Keyword
Latest Issue
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Hiroyuki TSUJIKAWA, Kenji SHIMAZAKI, Shozo HIRANO, Kazuhiro SATO, Masanori HIROFUJI, Junichi SHIMADA, Mitsumi ITO, Kiyohito MUKAI, "Power-Supply Noise Reduction with Design for Manufacturability" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3421-3428, December 2005, doi: 10.1093/ietfec/e88-a.12.3421.
Abstract: In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3421/_p
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@ARTICLE{e88-a_12_3421,
author={Hiroyuki TSUJIKAWA, Kenji SHIMAZAKI, Shozo HIRANO, Kazuhiro SATO, Masanori HIROFUJI, Junichi SHIMADA, Mitsumi ITO, Kiyohito MUKAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Power-Supply Noise Reduction with Design for Manufacturability},
year={2005},
volume={E88-A},
number={12},
pages={3421-3428},
abstract={In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).},
keywords={},
doi={10.1093/ietfec/e88-a.12.3421},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Power-Supply Noise Reduction with Design for Manufacturability
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3421
EP - 3428
AU - Hiroyuki TSUJIKAWA
AU - Kenji SHIMAZAKI
AU - Shozo HIRANO
AU - Kazuhiro SATO
AU - Masanori HIROFUJI
AU - Junichi SHIMADA
AU - Mitsumi ITO
AU - Kiyohito MUKAI
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3421
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).
ER -
English
