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[Author] Kazuhiro SATO(4hit)

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  • Analysis and Design of Aggregate Demand Response Systems Based on Controllability Open Access

    Kazuhiro SATO  Shun-ichi AZUMA  

     
    PAPER-Mathematical Systems Science

      Pubricized:
    2020/12/01
      Vol:
    E104-A No:6
      Page(s):
    940-948

    We address analysis and design problems of aggregate demand response systems composed of various consumers based on controllability to facilitate to design automated demand response machines that are installed into consumers to automatically respond to electricity price changes. To this end, we introduce a controllability index that expresses the worst-case error between the expected total electricity consumption and the electricity supply when the best electricity price is chosen. The analysis problem using the index considers how to maximize the controllability of the whole consumer group when the consumption characteristic of each consumer is not fixed. In contrast, the design problem considers the whole consumer group when the consumption characteristics of a part of the group are fixed. By solving the analysis problem, we first clarify how the controllability, average consumption characteristics of all consumers, and the number of selectable electricity prices are related. In particular, the minimum value of the controllability index is determined by the number of selectable electricity prices. Next, we prove that the design problem can be solved by a simple linear optimization. Numerical experiments demonstrate that our results are able to increase the controllability of the overall consumer group.

  • Controllability Analysis of Aggregate Demand Response System in Multiple Price-Change Situation

    Kazuhiro SATO  Shun-ichi AZUMA  

     
    PAPER

      Vol:
    E100-A No:2
      Page(s):
    376-384

    The paper studies controllability of an aggregate demand response system, i.e., the amount of the change of the total electric consumption in response to the change of the electric price, for real-time pricing (RTP). In order to quantify the controllability, this paper defines the controllability index as the lowest occurrence probability of the total electric consumption when the best possible the electric price is chosen. Then the paper formulates the problem which finds the consumer group maximizing the controllability index. The controllability problem becomes hard to solve as the number of consumers increases. To give a solution of the controllability problem, the article approximates the controllability index by the generalized central limit theorem. Using the approximated controllability index, the controllability problem can be reduced to a problem for solving nonlinear equations. Since the number of variables of the equations is independent of the number of consumers, an approximate solution of the controllability problem is obtained by numerically solving the equations.

  • An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs

    Kenji SHIMAZAKI  Makoto NAGATA  Mitsuya FUKAZAWA  Shingo MIYAHARA  Masaaki HIRATA  Kazuhiro SATOH  Hiroyuki TSUJIKAWA  

     
    PAPER

      Vol:
    E89-C No:11
      Page(s):
    1535-1543

    We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.

  • Power-Supply Noise Reduction with Design for Manufacturability

    Hiroyuki TSUJIKAWA  Kenji SHIMAZAKI  Shozo HIRANO  Kazuhiro SATO  Masanori HIROFUJI  Junichi SHIMADA  Mitsumi ITO  Kiyohito MUKAI  

     
    PAPER-Power/Ground Network

      Vol:
    E88-A No:12
      Page(s):
    3421-3428

    In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).