This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

This paper provides an investigation of power distribution network (PDN) performance by a full-wave prediction tool and by experimental measurements. A set of six real boards characterized by increasing complexity is considered in order to establish a solid base for behaviour understanding of printed circuit boards. How the growing complexity impacts on the board performance is investigated by measurements and by simulations. Strengths and weakness of PDN modeling by the full-wave software tool Microwave Studio are highlighted and discussed.

Developing LSIs with EMI suppression, particularly for use in automobiles, is important for improving warranties and customer acquisition. First, we describe that the measures against EMI noise caused by a X'tal oscillator are important. Next, we present a practical method for analyzing the noise with models of the inside and outside of a chip. In addition, we propose a within-chip measure against EMI noise that takes chip cost into account. The noise is suppressed by using an appropriate resistance and capacitance on the power line. Simulation results demonstrated the method's effectiveness in suppressing noise.

Sleep transistors such as MTCMOS and SCCMOS drastically reduce leakage current, but their ON resistances cause significant performance degradation. Larger sleep transistors reduce their ON resistances, but increase leakage current in a sleep mode. Decoupling capacitors beside sleep transistors reduce leakage current. Experimental results show that PMOS SCCMOS with a 4 pF decoupling capacitor reduces leakage current by 1/673 on a 64 bit adder in a 90 nm process.

In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1-13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).

This paper reports experimental results on far-field radiated emission for different on-chip chip power supply networks. Two types of test chips were developed as noise generators. One was with on-chip decoupling capacitance, and the other was without intentional on-chip decoupling capacitance. They were assembled in a CSP (Chip scale package). The effects of on-chip decoupling capacitance on far-field radiated emission were investigated for the operation of core logic circuits and output buffer circuits. Reduced radiated emission was observed for every harmonics for the operation of core logic circuits by the on-chip decoupling capacitance. While, reduced radiated emission was observed for the even-order harmonics for the operation of output buffer circuits due to the existence of on-chip decoupling capacitance.

This paper compares a stub and a decoupling capacitor for power supply noise reduction. A quarter-length stub attached to the power supply line of an LSI chip works as a band-eliminate filter, and suppresses the power supply bounce of the designed frequency. The conditions where the stub is more effective than the same-area decoupling capacitor are clarified. The stub will work more efficiently and on-chip integration will be possible on high frequency operation LSIs.

In this paper, we present an efficient method to budget on-chip decoupling capacitors (decaps) to optimize power delivery networks in an area efficient way. Our algorithm is based on an efficient gradient-based non-linear programming method for searching the solution. Our contributions are an efficient gradient computation method (time-domain merged adjoint network method) and a novel equivalent circuit modeling technique to speed up the optimization process. Experimental results demonstrate that the algorithm is capable of efficiently optimizing very large scale P/G networks.

This letter presents a novel method to design a power distribution network with highly accurate impedance characteristic. Based on the PBEC (path-based equivalent circuit) model and the network synthesis, the proposed design method exploits simple arithmetic expressions to calculate the electrical parameters of a power distribution network. It directly calculates and determines the size of on-chip decoupling capacitors, the size and location of off-chip decoupling capacitors, and the effective inductances of the package power bus. To evaluate the accuracy of the proposed method, it was applied to a test board with size of 12.5 cm 12.5 cm and with plane-to-plane distance of 200 µm. The proposed method successfully designed a power distribution network keeping its impedance characteristic under 1 Ω with frequency range of 100 kHz-1 GHz. The proposed design method requires negligible computation when compared with conventional PEEC (partial elements equivalent circuit) model-based design approaches, but the simulation results of both methods are almost identical. Consequently, the proposed method enables simple, fast and accurate design of power-distribution networks, which gives economic and practical solutions for commercial tools.

We have thoroughly investigated the effect of on-chip decoupling capacitors on the simultaneous switching noise (SSN) and the radiated emission. Furthermore, we have successfully demonstrated an efficient design method for on-chip decoupling capacitors on an 8-bit microcontroller without increasing the die size, which results in more than 10 dB of suppressed radiated emission.

This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.