IEICE TRANSACTIONS on Electronics
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
Summary :
This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.4 pp.560-567
- Publication Date
- 2013/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.560
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
- Category
Authors
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Jinmyoung KIM, Toru NAKURA, Koichiro ISHIBASHI, Makoto IKEDA, Kunihiro ASADA, "On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 4, pp. 560-567, April 2013, doi: 10.1587/transele.E96.C.560.
Abstract: This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.560/_p
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@ARTICLE{e96-c_4_560,
author={Jinmyoung KIM, Toru NAKURA, Koichiro ISHIBASHI, Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems},
year={2013},
volume={E96-C},
number={4},
pages={560-567},
abstract={This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.},
keywords={},
doi={10.1587/transele.E96.C.560},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 560
EP - 567
AU - Jinmyoung KIM
AU - Toru NAKURA
AU - Koichiro ISHIBASHI
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 2013
DO - 10.1587/transele.E96.C.560
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2013
AB - This paper presents a decoupling capacitance boosting method for the resonant supply noise reduction by fast voltage hopping of DVS systems. The proposed method utilizes a foot transistor as a switch between a conventional decoupling capacitor (decap) and GND. The switching controls of the foot transistor depending on the supply noise states achieve an effective noise reduction as well as fast settling time compared with the conventional passive decaps. The measurement results of a test chip fabricated in a 0.18 µm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.
ER -
English
