A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source

Kazuhiro SHOUNO; Tasuku HORI; Yukio ISHIBASHI

doi:10.1093/ietfec/e89-a.6.1533

A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source

Kazuhiro SHOUNO, Tasuku HORI, Yukio ISHIBASHI

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This paper proposes a linearized multiplier using the MOS transistors. The proposed circuit can be realized by adding two voltage shifters and some current mirrors to the conventional circuit. Especially, these additional voltage shifters can be saved when the proposed circuit is used as a transconductor. The proposed circuit is driven by a controlled tail current source. A technique to reduce the effect of the mobility reduction is proposed. First, the output current of the conventional transconductor is analytically derived and its problem is pointed out. Secondly, the proposed circuit is shown. The proposed method is accomplished by taking the mobility reduction into account. The validity of the proposed method is confirmed through both of Spice simulation and experiment. Finally, the proposed circuit is fabricated in the 1.2 µm CMOS process. The second-order and the third-order distortions are about -55 dB and -64 dB, respectively for a 0.5 Vp-p sinusoidal input signal.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.6 pp.1533-1539

Publication Date: 2006/06/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e89-a.6.1533

Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))

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Kazuhiro SHOUNO, Tasuku HORI, Yukio ISHIBASHI, "A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source" in IEICE TRANSACTIONS on Fundamentals, vol. E89-A, no. 6, pp. 1533-1539, June 2006, doi: 10.1093/ietfec/e89-a.6.1533.
Abstract: This paper proposes a linearized multiplier using the MOS transistors. The proposed circuit can be realized by adding two voltage shifters and some current mirrors to the conventional circuit. Especially, these additional voltage shifters can be saved when the proposed circuit is used as a transconductor. The proposed circuit is driven by a controlled tail current source. A technique to reduce the effect of the mobility reduction is proposed. First, the output current of the conventional transconductor is analytically derived and its problem is pointed out. Secondly, the proposed circuit is shown. The proposed method is accomplished by taking the mobility reduction into account. The validity of the proposed method is confirmed through both of Spice simulation and experiment. Finally, the proposed circuit is fabricated in the 1.2 µm CMOS process. The second-order and the third-order distortions are about -55 dB and -64 dB, respectively for a 0.5 Vp-p sinusoidal input signal.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.6.1533/_p

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@ARTICLE{e89-a_6_1533,
author={Kazuhiro SHOUNO, Tasuku HORI, Yukio ISHIBASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source},
year={2006},
volume={E89-A},
number={6},
pages={1533-1539},
abstract={This paper proposes a linearized multiplier using the MOS transistors. The proposed circuit can be realized by adding two voltage shifters and some current mirrors to the conventional circuit. Especially, these additional voltage shifters can be saved when the proposed circuit is used as a transconductor. The proposed circuit is driven by a controlled tail current source. A technique to reduce the effect of the mobility reduction is proposed. First, the output current of the conventional transconductor is analytically derived and its problem is pointed out. Secondly, the proposed circuit is shown. The proposed method is accomplished by taking the mobility reduction into account. The validity of the proposed method is confirmed through both of Spice simulation and experiment. Finally, the proposed circuit is fabricated in the 1.2 µm CMOS process. The second-order and the third-order distortions are about -55 dB and -64 dB, respectively for a 0.5 Vp-p sinusoidal input signal.},
keywords={},
doi={10.1093/ietfec/e89-a.6.1533},
ISSN={1745-1337},
month={June},}

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TY - JOUR
TI - A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1533
EP - 1539
AU - Kazuhiro SHOUNO
AU - Tasuku HORI
AU - Yukio ISHIBASHI
PY - 2006
DO - 10.1093/ietfec/e89-a.6.1533
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2006
AB - This paper proposes a linearized multiplier using the MOS transistors. The proposed circuit can be realized by adding two voltage shifters and some current mirrors to the conventional circuit. Especially, these additional voltage shifters can be saved when the proposed circuit is used as a transconductor. The proposed circuit is driven by a controlled tail current source. A technique to reduce the effect of the mobility reduction is proposed. First, the output current of the conventional transconductor is analytically derived and its problem is pointed out. Secondly, the proposed circuit is shown. The proposed method is accomplished by taking the mobility reduction into account. The validity of the proposed method is confirmed through both of Spice simulation and experiment. Finally, the proposed circuit is fabricated in the 1.2 µm CMOS process. The second-order and the third-order distortions are about -55 dB and -64 dB, respectively for a 0.5 Vp-p sinusoidal input signal.
ER -