A wideband noise-cancelling receiver front-end is proposed in this brief. As a basic architecture, a low-noise transconductance amplifier, a passive mixer, and a transimpedance amplifier are employed to compose the wideband receiver. To achieve wideband input matching for the transconductor, a global feedback method is adopted. Since the wideband receiver has to minimize linearity degradation if a large blocker signal exists out-of-band, a linearization technique is applied for the transconductor circuit. The linearization cancels third-order intermodulation distortion components and increases linearity; however, the additional circuits used in linearization generate excessive noise. A noise-cancelling architecture that employs an auxiliary path cancels noise signals generated in the main path. The designed receiver front-end is fabricated using a 65-nm CMOS process. The receiver operates in the frequency range of 25 MHz-2 GHz with a gain of 49.7 dB. The in-band input-referred third-order intercept point is improved by 12.3 dB when the linearization is activated, demonstrating the effectiveness of the linearization technique.

In this paper, a differential input/output linear MOS transconductor using an adaptively biasing technique is proposed. The proposed transconductor based on a differential pair is linearized by employing an adaptively biasing circuit. The linear characteristic of the individual differential output currents are obtained by introducing the adaptively biased currents to terminate the differential output terminals. Using the proposed technique, the common-mode rejection ration (CMRR) becomes high. Simulation results show that the proposed technique is effective for improvement of the linearity and other performances.

High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.

A CMOS transconductor for multi-mode application is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier, which operates in the weak inversion region, provides a wide transconductance tuning range without degrading the linearity. The transconductor was designed and fabricated in the TSMC 0.18-µm CMOS process. The results show the transconductance tuning ratio of 23 and the IM3 performance of -68.5 dB.

This paper describes a novel high-Q active inductor circuit configuration composed of an operational transconductance amplifier (OTA) and an input RC network. Due to the phase rotation made by the input RC network, the active inductor circuit provides high-Q inductive impedance at higher frequencies. According to circuit simulation with design-kit of a 90-GHz-fT SiGe HBT technology, an inductance of more than 0.53 nH and Q of more than 80 can be obtained at quasi-millimeter-wave frequency, 24 GHz. The Q value is tunable by controlling the transconductance of the OTA. These features are also ensured by means of measurements of fabricated active inductor circuit. Since the active inductor circuit needs small chip area, which is 25% of a conventional passive inductor, the proposed active inductor contributes to implement a cost-effective high-Q notch filter for frequencies up to quasi-millimeter-wave frequencies.

A novel linear transconductor using translinear cells is proposed. It consists of a voltage follower, a resistor, and a current follower. SPICE simulations using an 8 GHz bipolar transistor-array parameter show that the linear transconductor with a transconductance of 1 mS exhibits a linearity error of less than 0.75% over an input voltage range of 1 V for a supply voltage of 2.0 V. The temperature coefficient of the transconductance is less than 124 ppm/. The -3-dB frequency of the transconductance is more than 4.5 GHz. Applying the linear transconductor as a building block, the design of a bandpass filter with center frequency of 85 MHz and Q-factor of 80 is presented.

A linear CMOS transconductor is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting to avoid the body effect. To annihilate the non-linear voltage terms, the substrate-bias effect of MOS transistors is treated more accurately in our design. Consequently, the non-linearity of the large-signal transconductance is reduced. The fabricated circuit occupies an area of 245 µm176 µm ( ≈approx 0.043 mm2) and dissipates 0.87 mW from a 3.3 V supply. For an input of 1 Vp-p, the measured output total harmonic distortion is less than 1.2%. The transconductance varies by less than 0.5% in the input range.

A new method to reduce power consumption of a linear transconductor is proposed in this paper. The minimum tail current for the operation of the transconductor is supplied by a new current source circuit. The proposed circuit is based on a dynamic biasing current technique. Results of SPICE simulation show that the proposed technique is very effective to reduce power consumption of the transconductor.

This paper proposes a linearized multiplier using the MOS transistors. The proposed circuit can be realized by adding two voltage shifters and some current mirrors to the conventional circuit. Especially, these additional voltage shifters can be saved when the proposed circuit is used as a transconductor. The proposed circuit is driven by a controlled tail current source. A technique to reduce the effect of the mobility reduction is proposed. First, the output current of the conventional transconductor is analytically derived and its problem is pointed out. Secondly, the proposed circuit is shown. The proposed method is accomplished by taking the mobility reduction into account. The validity of the proposed method is confirmed through both of Spice simulation and experiment. Finally, the proposed circuit is fabricated in the 1.2 µm CMOS process. The second-order and the third-order distortions are about -55 dB and -64 dB, respectively for a 0.5 Vp-p sinusoidal input signal.

A four-quadrant-input linear transconductor generating a product or a product sum current is proposed. The proposed circuit eliminates the influence of channel length modulation and expands a dynamic input voltage range. As an application of the proposed circuit, the four-quadrant analog multiplier is designed. The four-quadrant analog multiplier consists of the proposed circuit, an input circuit and a class AB current buffer. HSPICE simulation results with 0.35 µm n-well single CMOS process parameter are shown in order to evaluate the proposed circuit.

Linearity of a transconductor with a theoretical linear characteristic is deteriorated by mobility degradation, in practice. In this paper, a technique to improve the linearity by combining a source-coupled pair with the transconductor is proposed. The proposed transconductor is the circuit that the deteriorated linearity of the conventional part is compensated by the transconductance characteristic of the source-coupled pair. In order to confirm the validity of the proposed technique, SPICE simulation is carried out. The transconductance change ratio of the proposed technique is about 1% and is 1/10 or less of the conventional circuit.

In this paper we report a 3rd-order Gm-C filter based on pseudo-differential continuous-time transconductors for applications in low-voltage systems over VHF range. By using a 0.18 µm pure digital CMOS process, a prototype low pass filter with -3 dB frequency programmable from 38 MHz to 213 MHz confirms the feasibility of the proposed filter in applications such as data storage systems.

In a direct conversion receiver for mobile communication, it is important to reduce power dissipation. Because a low pass filter in a direct conversion receiver must suppress adjacent channel signals, a high order and high power dissipation is often required in the low pass filter. We propose a new phase compensation technique suitable for a low power transconductor used in a GmC filter as a low pass filter. The new phase compensation technique reduces 10% of power dissipation.

A new bipolar linear transconductor for low-voltage low-power signal processing is proposed. The proposed circuit has larger input linear range and smaller power dissipation when compared with the conventional bipolar linear transconductor. The experimental results show that the transconductor with a transconductance of 50 µS has a linearity error of less than 0.02% over an input voltage range of 2.1 V at supply voltages of 3 V. The power dissipation of the transconductor is 3.15 mW.

A linear-in-dB gain-control amplifier for direct conversion systems employs linearized transconductors in a core amp, a dc offset canceler, and a gain control circuit. The offset compensation circuit achieves a constant corner frequency over a gain range of 14 to 76 dB by simultaneous tuning of the transconductors.

A Gm-C filter using multiple-output transconductors suitable for reducing the chip area and power consumption is presented. The novel multiple-output transconductor is based on a translinear gain cell with a linearized input stage. Making good use of the linearized input stage, a simple common-mode feedback is also proposed for this multiple-output transconductor. Using the proposed technique, a 5th-order lowpass filter with two transmission zeros was designed and fabricated as a main part of a lowpass channel selection filter for UMTS receivers. A channel of the filter consumes 7 mA from a 2.7 V power supply and the integrated input-referred noise was 21 dBuV with 20 dB pass band gain. The proposed multiple-output technique saves roughly half the number of transconductors compared with the typical active ladder filter design. The proposed multiple-output transconductors achieve linearization and effective reduction while saving linearized input stages. They are suitable for a filter with small power consumption and small area.

A fully balanced (FB) transconductor using two multi-input single-ended (SE) CMOS transconductors is proposed, where the transconductors use MOS transitors operating in a triode region for achieving a wide linear input-range. SE circuits are easier to design than differential circuits and inherently reject common-mode (CM) signals. The multi-input structure is used to make a CM feedback loop and to determine an output CM voltage. A high-output-resistance current mirror is used in converting a differential signal to a single-ended signal in order to achieve a high common-mode rejection ratio (CMRR) and a high output-resistance of the transconductor. The FB transconductor achieves a 2-Vpp linear input range at a 2.5-V power supply and consumes 1.74 mA. The output resistance of the FB transconductor is 2 MΩ. It operates at 2 V with a linear input-range of 1.2 Vpp and at 1.6 V with a linear input-range of 0.9 Vpp. A 2.5-V 2.5-MHz FB Gm-C filter using the FB transconductors achieved a CMRR of 45 dB and a passband IIP3 of 32 dBm.

Low-voltage technique for IC is getting one of the most important matters. It is quite difficult to realize a filter which can operate at 1 V or less because the base-emitter voltage of transistors can hardly be reduced. A design of a low-voltage continuous-time filter is presented in this paper. The basic building block of the filter is a pseudo-differential transconductor which has no tail current source. Therefore, the operating voltage is lower than that of an emitter-coupled pair. However, the common-mode (CM) gain of the transconductor is quite high and the CMRR is low. In order to reduce the CM gain, a CM feedback circuit is employed. The transconductance characteristic is expressed as the function of hyperbolic cosine. The designed filter is a fifth-order gyrator-C filter. The transconductor and the filter which has a fifth-order Butterworth lowpass characteristic are demonstrated by PSpice simulation. Transconductance characteristic, CMRR and stability of the transconductor are confirmed through the simulation. In the analysis of the filter, frequency response and offset voltage are examined. It is shown that the filter which has corner frequency of the order of megahertz can operate at a 1 V supply voltage.

A novel CMOS half-wave rectifying transconductor is presented. The proposed circuit utilizes a simple new cascode current subtracter which is obtained from conventional cascode current mirror by a judicious reconfiguration to yield additional subtrahend signal path. The simulated DC transfer characteristics is highly linear with 1.1% linearity error up to 1.5V differential input voltage and the blunt corner at zero-crossing is 20mV. The output resistance is greater than 23MΩ and the total harmonic distortions at 100kHz with 1.5Vp-p in the positive half cycle are better than -46.5dB. The usable operating frequencies are up to 10MHz with maximum peak-to-peak input voltage and 75µW power consumption.

A new linearization technique of a transconductor is presented. The linearization is realized by using a differential current amplifier with an emitter-coupled pair. A specific value of the linearization parameter gives a maximally flat or an equiripple characteristic. Deviations from the theoretical characteristic can be adjusted by tuning the tail current of the emitter-coupled pair. The proposed technique is demonstrated by PSPICE simulation.