Compact Test Sequences for Scan-Based Sequential Circuits

Hiroyuki HIGUCHI; Kiyoharu HAMAGUCHI; Shuzo YAJIMA

Compact Test Sequences for Scan-Based Sequential Circuits

Hiroyuki HIGUCHI, Kiyoharu HAMAGUCHI, Shuzo YAJIMA

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Full scan design of sequential circuits results in greatly reducing the cost of their test generation. However, it introduces the extra expense of many test clocks to control and observe the values of flip-flops because of the need to shift values for the flip-flops into the scan panh. In this paper we propose a new method of generating compact test sequences for scan-based sequential circuits on the assumption that the number of shift clocks is allowed to vary for each test vector. The method is based on Boolean function manipulation using a shared binary decision diagram (SBDD). Although the test generation algorithm is basically for general sequential circuits, the computational cost is much lower for scan-based sequential circuits than for non-scanbased sequential circuits because the length of a test sequence for each fault is limited. Experimental results show that, for all the tested circuits, test sequences generated by the method require much smaller number of test clocks than compact or minimum test sets for combinational logic part of scan-based sequential circuits. The reduction rate was 48% on the average in the experiments.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.10 pp.1676-1683

Publication Date: 1993/10/25

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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Hiroyuki HIGUCHI, Kiyoharu HAMAGUCHI, Shuzo YAJIMA, "Compact Test Sequences for Scan-Based Sequential Circuits" in IEICE TRANSACTIONS on Fundamentals, vol. E76-A, no. 10, pp. 1676-1683, October 1993, doi: .
Abstract: Full scan design of sequential circuits results in greatly reducing the cost of their test generation. However, it introduces the extra expense of many test clocks to control and observe the values of flip-flops because of the need to shift values for the flip-flops into the scan panh. In this paper we propose a new method of generating compact test sequences for scan-based sequential circuits on the assumption that the number of shift clocks is allowed to vary for each test vector. The method is based on Boolean function manipulation using a shared binary decision diagram (SBDD). Although the test generation algorithm is basically for general sequential circuits, the computational cost is much lower for scan-based sequential circuits than for non-scanbased sequential circuits because the length of a test sequence for each fault is limited. Experimental results show that, for all the tested circuits, test sequences generated by the method require much smaller number of test clocks than compact or minimum test sets for combinational logic part of scan-based sequential circuits. The reduction rate was 48% on the average in the experiments.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e76-a_10_1676/_p

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@ARTICLE{e76-a_10_1676,
author={Hiroyuki HIGUCHI, Kiyoharu HAMAGUCHI, Shuzo YAJIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Compact Test Sequences for Scan-Based Sequential Circuits},
year={1993},
volume={E76-A},
number={10},
pages={1676-1683},
abstract={Full scan design of sequential circuits results in greatly reducing the cost of their test generation. However, it introduces the extra expense of many test clocks to control and observe the values of flip-flops because of the need to shift values for the flip-flops into the scan panh. In this paper we propose a new method of generating compact test sequences for scan-based sequential circuits on the assumption that the number of shift clocks is allowed to vary for each test vector. The method is based on Boolean function manipulation using a shared binary decision diagram (SBDD). Although the test generation algorithm is basically for general sequential circuits, the computational cost is much lower for scan-based sequential circuits than for non-scanbased sequential circuits because the length of a test sequence for each fault is limited. Experimental results show that, for all the tested circuits, test sequences generated by the method require much smaller number of test clocks than compact or minimum test sets for combinational logic part of scan-based sequential circuits. The reduction rate was 48% on the average in the experiments.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Compact Test Sequences for Scan-Based Sequential Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1676
EP - 1683
AU - Hiroyuki HIGUCHI
AU - Kiyoharu HAMAGUCHI
AU - Shuzo YAJIMA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E76-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1993
AB - Full scan design of sequential circuits results in greatly reducing the cost of their test generation. However, it introduces the extra expense of many test clocks to control and observe the values of flip-flops because of the need to shift values for the flip-flops into the scan panh. In this paper we propose a new method of generating compact test sequences for scan-based sequential circuits on the assumption that the number of shift clocks is allowed to vary for each test vector. The method is based on Boolean function manipulation using a shared binary decision diagram (SBDD). Although the test generation algorithm is basically for general sequential circuits, the computational cost is much lower for scan-based sequential circuits than for non-scanbased sequential circuits because the length of a test sequence for each fault is limited. Experimental results show that, for all the tested circuits, test sequences generated by the method require much smaller number of test clocks than compact or minimum test sets for combinational logic part of scan-based sequential circuits. The reduction rate was 48% on the average in the experiments.
ER -