Embedded Memory Array Testing Using a Scannable Configuration

Seiken YANO, Nagisa ISHIURA

Summary :

We have previously proposed a scannable memory configuration which is useful in testing logic blocks around memory arrays. Although the configuration is supposed to be effective in testing the memory array itself by its frequent read/write access during the scan operation, it has not been theoretically shown what types of faults can be detected. In this paper, from a viewpoint of memory testing, we investigate the testability of the scannable memory configuration and propose a memory array test using the scan path. It is shown that we can detect (1) all stuck-at faults in memory cells, (2) all stuck-at faults in address decoders, (3) all stuck-at faults in read/write logic, (4) static, dynamic and 2-coupling faults between memory cells of adjacent words, and (5) static coupling faults between memory cells in the same word. The test can be accomplished simply by comparing scan-in data and scan-out data. The test vector is 20ms bit long, where m is the number of words of the memory array under test and s is the total scan path length.

• Publication: IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.10 pp.1934-1944
• Publication Date: 1997/10/25
• Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Authors

Seiken YANO
Nagisa ISHIURA

Keyword

scannable memory configuration,  memory array testing,  design-for-testability,  scan design