IEICE TRANSACTIONS on Fundamentals
Application of Full Scan Design to Embedded Memory Arrays
Summary :
This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.3 pp.514-520
- Publication Date
- 1997/03/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
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Seiken YANO, Katsutoshi AKAGI, Hiroki INOHARA, Nagisa ISHIURA, "Application of Full Scan Design to Embedded Memory Arrays" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 3, pp. 514-520, March 1997, doi: .
Abstract: This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_3_514/_p
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@ARTICLE{e80-a_3_514,
author={Seiken YANO, Katsutoshi AKAGI, Hiroki INOHARA, Nagisa ISHIURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Application of Full Scan Design to Embedded Memory Arrays},
year={1997},
volume={E80-A},
number={3},
pages={514-520},
abstract={This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Application of Full Scan Design to Embedded Memory Arrays
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 514
EP - 520
AU - Seiken YANO
AU - Katsutoshi AKAGI
AU - Hiroki INOHARA
AU - Nagisa ISHIURA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1997
AB - This paper describes the design and evaluation of fully scannable embedded memory arrays. A memory array, such as a register file, is made scannable by adding a small auxiliary circuit including a counter and multiplexers. Plural memory arrays can be chained into a single scan path along with ordinary flip-flops. Detailed configuration and implementation of the scannable CMOS and bipolar LCML register file macros are discussed. The overhead ratio of the CMOS register file macro with 16-word by 16-bit results in an 8.6% transistor count and a 6.4% die area. The access time overhaead is 7.8% and the set-up time increases by about 50ps. Bipolar LCML register file macros have been applied to gate array LSIs which have successfully achieved average stuck-at fault coverage of 99.2%.
ER -
English
