IEICE TRANSACTIONS on Fundamentals
High-Swing CMOS Cascode Current Mirror Operating with 1V Power Supply Voltage
Summary :
A high performance, high-swing CMOS cascode current mirror operating with 1V power supply voltage and using standard CMOS technology is presented. The present circuit employs PMOS source-coupled pair as voltage level shifter to reduce the power supply voltage requirement. The additional advantages of the use of the source-coupled pair are the improved output resistance and the automatic adaptive biasing, thereby enabling the high-swing of output terminal, when used in the cascode configuration. An analytical discussion of the circuit is carried out and the results are confirmed by SPICE simulation. SPICE simulation results show that the input voltage requirement is 370mV and the minimum output voltage requirement is 273mV at the maximum input current of 40µA, whose requirements decrease with decreasing input currens. The output resistance is shown to be greater than 4MΩ at the maximum output current of 40µA, which increases with decreasing output currents. The -3dB bandwidth is shown to be greater than 400MHz and the total harmonic distortion better than -54.34dB at 100kHz at the maximum peak-to-peak input current swing of 40µA. The present circuit will be useful for the low voltage, low power, high-performance mixed analog/digital signal processing.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E80-A No.6 pp.1083-1091
- Publication Date
- 1997/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Analog Signal Processing
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Sibum JUN, Dae Mann KIM, "High-Swing CMOS Cascode Current Mirror Operating with 1V Power Supply Voltage" in IEICE TRANSACTIONS on Fundamentals,
vol. E80-A, no. 6, pp. 1083-1091, June 1997, doi: .
Abstract: A high performance, high-swing CMOS cascode current mirror operating with 1V power supply voltage and using standard CMOS technology is presented. The present circuit employs PMOS source-coupled pair as voltage level shifter to reduce the power supply voltage requirement. The additional advantages of the use of the source-coupled pair are the improved output resistance and the automatic adaptive biasing, thereby enabling the high-swing of output terminal, when used in the cascode configuration. An analytical discussion of the circuit is carried out and the results are confirmed by SPICE simulation. SPICE simulation results show that the input voltage requirement is 370mV and the minimum output voltage requirement is 273mV at the maximum input current of 40µA, whose requirements decrease with decreasing input currens. The output resistance is shown to be greater than 4MΩ at the maximum output current of 40µA, which increases with decreasing output currents. The -3dB bandwidth is shown to be greater than 400MHz and the total harmonic distortion better than -54.34dB at 100kHz at the maximum peak-to-peak input current swing of 40µA. The present circuit will be useful for the low voltage, low power, high-performance mixed analog/digital signal processing.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e80-a_6_1083/_p
Copy
@ARTICLE{e80-a_6_1083,
author={Sibum JUN, Dae Mann KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Swing CMOS Cascode Current Mirror Operating with 1V Power Supply Voltage},
year={1997},
volume={E80-A},
number={6},
pages={1083-1091},
abstract={A high performance, high-swing CMOS cascode current mirror operating with 1V power supply voltage and using standard CMOS technology is presented. The present circuit employs PMOS source-coupled pair as voltage level shifter to reduce the power supply voltage requirement. The additional advantages of the use of the source-coupled pair are the improved output resistance and the automatic adaptive biasing, thereby enabling the high-swing of output terminal, when used in the cascode configuration. An analytical discussion of the circuit is carried out and the results are confirmed by SPICE simulation. SPICE simulation results show that the input voltage requirement is 370mV and the minimum output voltage requirement is 273mV at the maximum input current of 40µA, whose requirements decrease with decreasing input currens. The output resistance is shown to be greater than 4MΩ at the maximum output current of 40µA, which increases with decreasing output currents. The -3dB bandwidth is shown to be greater than 400MHz and the total harmonic distortion better than -54.34dB at 100kHz at the maximum peak-to-peak input current swing of 40µA. The present circuit will be useful for the low voltage, low power, high-performance mixed analog/digital signal processing.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - High-Swing CMOS Cascode Current Mirror Operating with 1V Power Supply Voltage
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1083
EP - 1091
AU - Sibum JUN
AU - Dae Mann KIM
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E80-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1997
AB - A high performance, high-swing CMOS cascode current mirror operating with 1V power supply voltage and using standard CMOS technology is presented. The present circuit employs PMOS source-coupled pair as voltage level shifter to reduce the power supply voltage requirement. The additional advantages of the use of the source-coupled pair are the improved output resistance and the automatic adaptive biasing, thereby enabling the high-swing of output terminal, when used in the cascode configuration. An analytical discussion of the circuit is carried out and the results are confirmed by SPICE simulation. SPICE simulation results show that the input voltage requirement is 370mV and the minimum output voltage requirement is 273mV at the maximum input current of 40µA, whose requirements decrease with decreasing input currens. The output resistance is shown to be greater than 4MΩ at the maximum output current of 40µA, which increases with decreasing output currents. The -3dB bandwidth is shown to be greater than 400MHz and the total harmonic distortion better than -54.34dB at 100kHz at the maximum peak-to-peak input current swing of 40µA. The present circuit will be useful for the low voltage, low power, high-performance mixed analog/digital signal processing.
ER -
English
