IEICE TRANSACTIONS on Fundamentals
A Low-Power DSP Core Architecture for Low Bitrate Speech Codec
Summary :
A VLSI implementation of a low-power DSP core is described, which is dedicated to the G. 723. 1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The main attempt is focused on lowering the clock frequency, and therefore on reducing the total power consumption, at the cost of a fairly small increase of chip area. The proposed DSP architecture has been integrated in the total area of 7. 75 mm2 by using a 0. 35 µm CMOS technology, which can operate at 10 MHz with the dissipation of 44. 9 mW from a single 3 V supply.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.8 pp.1616-1621
- Publication Date
- 1998/08/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on Digital Signal Processing)
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Hiroyuki OKUHATA, Morgan H. MIKI, Takao ONOYE, Isao SHIRAKAWA, "A Low-Power DSP Core Architecture for Low Bitrate Speech Codec" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 8, pp. 1616-1621, August 1998, doi: .
Abstract: A VLSI implementation of a low-power DSP core is described, which is dedicated to the G. 723. 1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The main attempt is focused on lowering the clock frequency, and therefore on reducing the total power consumption, at the cost of a fairly small increase of chip area. The proposed DSP architecture has been integrated in the total area of 7. 75 mm2 by using a 0. 35 µm CMOS technology, which can operate at 10 MHz with the dissipation of 44. 9 mW from a single 3 V supply.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_8_1616/_p
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@ARTICLE{e81-a_8_1616,
author={Hiroyuki OKUHATA, Morgan H. MIKI, Takao ONOYE, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low-Power DSP Core Architecture for Low Bitrate Speech Codec},
year={1998},
volume={E81-A},
number={8},
pages={1616-1621},
abstract={A VLSI implementation of a low-power DSP core is described, which is dedicated to the G. 723. 1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The main attempt is focused on lowering the clock frequency, and therefore on reducing the total power consumption, at the cost of a fairly small increase of chip area. The proposed DSP architecture has been integrated in the total area of 7. 75 mm2 by using a 0. 35 µm CMOS technology, which can operate at 10 MHz with the dissipation of 44. 9 mW from a single 3 V supply.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A Low-Power DSP Core Architecture for Low Bitrate Speech Codec
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1616
EP - 1621
AU - Hiroyuki OKUHATA
AU - Morgan H. MIKI
AU - Takao ONOYE
AU - Isao SHIRAKAWA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 1998
AB - A VLSI implementation of a low-power DSP core is described, which is dedicated to the G. 723. 1 low bitrate speech codec. A number of sophisticated DSP microarchitectures are devised mainly on dual multiply accumulators, rounding and saturation mechanisms, and two-banked on-chip memory. The main attempt is focused on lowering the clock frequency, and therefore on reducing the total power consumption, at the cost of a fairly small increase of chip area. The proposed DSP architecture has been integrated in the total area of 7. 75 mm2 by using a 0. 35 µm CMOS technology, which can operate at 10 MHz with the dissipation of 44. 9 mW from a single 3 V supply.
ER -
English
