IEICE TRANSACTIONS on Fundamentals
Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
Summary :
We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 3 circuits. The power dissipation is reduced by 75% maximum and 60% on average without delay increase. Compared with discrete cell sizing, the proposed method reduces power dissipation furthermore by 30% on average.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.11 pp.2769-2777
- Publication Date
- 2001/11/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Optimization of Power and Timing
Authors
Keyword
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Masanori HASHIMOTO, Hidetoshi ONODERA, "Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2769-2777, November 2001, doi: .
Abstract: We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 3 circuits. The power dissipation is reduced by 75% maximum and 60% on average without delay increase. Compared with discrete cell sizing, the proposed method reduces power dissipation furthermore by 30% on average.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2769/_p
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@ARTICLE{e84-a_11_2769,
author={Masanori HASHIMOTO, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design},
year={2001},
volume={E84-A},
number={11},
pages={2769-2777},
abstract={We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 3 circuits. The power dissipation is reduced by 75% maximum and 60% on average without delay increase. Compared with discrete cell sizing, the proposed method reduces power dissipation furthermore by 30% on average.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2769
EP - 2777
AU - Masanori HASHIMOTO
AU - Hidetoshi ONODERA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - We propose a transistor sizing method that downsizes MOSFETs inside a cell to eliminate redundancy of cell-based circuits as much as possible. Our method reduces power dissipation of detail-routed circuits while preserving interconnects. The effectiveness of our method is experimentally evaluated using 3 circuits. The power dissipation is reduced by 75% maximum and 60% on average without delay increase. Compared with discrete cell sizing, the proposed method reduces power dissipation furthermore by 30% on average.
ER -
English
