IEICE TRANSACTIONS on Fundamentals
Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications
Summary :
In portable applications such as W-CDMA cell phones, high performance and low standby leakage are both required. We propose an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are newly introduced. MT cells are assigned to critical paths to speed up, while High-Vth cells are assigned to non-critical paths to reduce leakage. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core for W-CDMA baseband LSI. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2667-2673
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Optimization of Power and Timing
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Kimiyoshi USAMI, Naoyuki KAWABE, Masayuki KOIZUMI, Katsuhiro SETA, Toshiyuki FURUSAWA, "Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2667-2673, December 2002, doi: .
Abstract: In portable applications such as W-CDMA cell phones, high performance and low standby leakage are both required. We propose an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are newly introduced. MT cells are assigned to critical paths to speed up, while High-Vth cells are assigned to non-critical paths to reduce leakage. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core for W-CDMA baseband LSI. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2667/_p
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@ARTICLE{e85-a_12_2667,
author={Kimiyoshi USAMI, Naoyuki KAWABE, Masayuki KOIZUMI, Katsuhiro SETA, Toshiyuki FURUSAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications},
year={2002},
volume={E85-A},
number={12},
pages={2667-2673},
abstract={In portable applications such as W-CDMA cell phones, high performance and low standby leakage are both required. We propose an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are newly introduced. MT cells are assigned to critical paths to speed up, while High-Vth cells are assigned to non-critical paths to reduce leakage. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core for W-CDMA baseband LSI. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2667
EP - 2673
AU - Kimiyoshi USAMI
AU - Naoyuki KAWABE
AU - Masayuki KOIZUMI
AU - Katsuhiro SETA
AU - Toshiyuki FURUSAWA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - In portable applications such as W-CDMA cell phones, high performance and low standby leakage are both required. We propose an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are newly introduced. MT cells are assigned to critical paths to speed up, while High-Vth cells are assigned to non-critical paths to reduce leakage. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core for W-CDMA baseband LSI. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.
ER -
English
