Experimental Study on Cell-Base High-Performance Datapath Design

Masanori HASHIMOTO; Yoshiteru HAYASHI; Hidetoshi ONODERA

Experimental Study on Cell-Base High-Performance Datapath Design

Masanori HASHIMOTO, Yoshiteru HAYASHI, Hidetoshi ONODERA

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This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistor-level circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35 µm technology. From the experimental results, we can scarcely observe that manual cell placement contributes to improve circuit performance. On the other hand, transistor-level circuit optimization is so effective that circuit delay is reduced by 11-20% and power dissipation decreases to 42-62%. We can see that, in the case of cell-base design, transistor-level optimization is also important as well as in the case of custom design, whereas cell-base bit-slice layout has less importance to circuit performance.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3204-3207

Publication Date: 2003/12/01

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Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)

Category: IP Design

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Masanori HASHIMOTO, Yoshiteru HAYASHI, Hidetoshi ONODERA, "Experimental Study on Cell-Base High-Performance Datapath Design" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 12, pp. 3204-3207, December 2003, doi: .
Abstract: This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistor-level circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35 µm technology. From the experimental results, we can scarcely observe that manual cell placement contributes to improve circuit performance. On the other hand, transistor-level circuit optimization is so effective that circuit delay is reduced by 11-20% and power dissipation decreases to 42-62%. We can see that, in the case of cell-base design, transistor-level optimization is also important as well as in the case of custom design, whereas cell-base bit-slice layout has less importance to circuit performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3204/_p

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@ARTICLE{e86-a_12_3204,
author={Masanori HASHIMOTO, Yoshiteru HAYASHI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Experimental Study on Cell-Base High-Performance Datapath Design},
year={2003},
volume={E86-A},
number={12},
pages={3204-3207},
abstract={This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistor-level circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35 µm technology. From the experimental results, we can scarcely observe that manual cell placement contributes to improve circuit performance. On the other hand, transistor-level circuit optimization is so effective that circuit delay is reduced by 11-20% and power dissipation decreases to 42-62%. We can see that, in the case of cell-base design, transistor-level optimization is also important as well as in the case of custom design, whereas cell-base bit-slice layout has less importance to circuit performance.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Experimental Study on Cell-Base High-Performance Datapath Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3204
EP - 3207
AU - Masanori HASHIMOTO
AU - Yoshiteru HAYASHI
AU - Hidetoshi ONODERA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistor-level circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35 µm technology. From the experimental results, we can scarcely observe that manual cell placement contributes to improve circuit performance. On the other hand, transistor-level circuit optimization is so effective that circuit delay is reduced by 11-20% and power dissipation decreases to 42-62%. We can see that, in the case of cell-base design, transistor-level optimization is also important as well as in the case of custom design, whereas cell-base bit-slice layout has less importance to circuit performance.
ER -