IEICE TRANSACTIONS on Fundamentals
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Summary :
Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.12 pp.3128-3135
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.3128
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verfication
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Yoshinobu HIGAMI, Kewal K. SALUJA, Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, "Addressing Defect Coverage through Generating Test Vectors for Transistor Defects" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3128-3135, December 2009, doi: 10.1587/transfun.E92.A.3128.
Abstract: Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3128/_p
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@ARTICLE{e92-a_12_3128,
author={Yoshinobu HIGAMI, Kewal K. SALUJA, Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Addressing Defect Coverage through Generating Test Vectors for Transistor Defects},
year={2009},
volume={E92-A},
number={12},
pages={3128-3135},
abstract={Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.},
keywords={},
doi={10.1587/transfun.E92.A.3128},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3128
EP - 3135
AU - Yoshinobu HIGAMI
AU - Kewal K. SALUJA
AU - Hiroshi TAKAHASHI
AU - Shin-ya KOBAYASHI
AU - Yuzo TAKAMATSU
PY - 2009
DO - 10.1587/transfun.E92.A.3128
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.
ER -
English
