IEICE TRANSACTIONS on Fundamentals
Reduction of Area per Good Die for SoC Memory Built-In Self-Test
Summary :
To reduce the manufacturing cost of SoCs with many embedded SRAMs, we propose a scheme to reduce the area per good die for the SoC memory built-in self-test (MBIST). We first propose BIST hardware overhead reduction by application of an encoder-based comparator. For the repair of a faulty SRAM module with 2-D redundancy, we propose spare assignement algorithm. Based on an existing range-cheking-first algorithm (RCFA), we propose assign-all-row-RCFA (A-RCFA) which assign unused spare rows to faulty ones, in order to suppress the degradation of repair rate due to compressed fail location information output from the encoder-based comparator. Then, considering that an SoC has many SRAM modules, we propose a heuristic algorithm based on iterative improvement algorithm (IIA), which determines whether each SRAM should have a spare row or not, in order to minimize area per a good die. Experimental results on practical scale benchmark SoCs with more than 1,000 SRAM modules indicate that encoder-based comparators reduce hardware overhead by about 50% compared to traditional ones, and that combining the IIA-based algorithm for determining redundancy architecture with the encoder-based comparator effectively reduces the area per good die.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.12 pp.2463-2471
- Publication Date
- 2010/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.2463
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Masayuki ARAI, Tatsuro ENDO, Kazuhiko IWASAKI, Michinobu NAKAO, Iwao SUZUKI, "Reduction of Area per Good Die for SoC Memory Built-In Self-Test" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2463-2471, December 2010, doi: 10.1587/transfun.E93.A.2463.
Abstract: To reduce the manufacturing cost of SoCs with many embedded SRAMs, we propose a scheme to reduce the area per good die for the SoC memory built-in self-test (MBIST). We first propose BIST hardware overhead reduction by application of an encoder-based comparator. For the repair of a faulty SRAM module with 2-D redundancy, we propose spare assignement algorithm. Based on an existing range-cheking-first algorithm (RCFA), we propose assign-all-row-RCFA (A-RCFA) which assign unused spare rows to faulty ones, in order to suppress the degradation of repair rate due to compressed fail location information output from the encoder-based comparator. Then, considering that an SoC has many SRAM modules, we propose a heuristic algorithm based on iterative improvement algorithm (IIA), which determines whether each SRAM should have a spare row or not, in order to minimize area per a good die. Experimental results on practical scale benchmark SoCs with more than 1,000 SRAM modules indicate that encoder-based comparators reduce hardware overhead by about 50% compared to traditional ones, and that combining the IIA-based algorithm for determining redundancy architecture with the encoder-based comparator effectively reduces the area per good die.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2463/_p
Copy
@ARTICLE{e93-a_12_2463,
author={Masayuki ARAI, Tatsuro ENDO, Kazuhiko IWASAKI, Michinobu NAKAO, Iwao SUZUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Reduction of Area per Good Die for SoC Memory Built-In Self-Test},
year={2010},
volume={E93-A},
number={12},
pages={2463-2471},
abstract={To reduce the manufacturing cost of SoCs with many embedded SRAMs, we propose a scheme to reduce the area per good die for the SoC memory built-in self-test (MBIST). We first propose BIST hardware overhead reduction by application of an encoder-based comparator. For the repair of a faulty SRAM module with 2-D redundancy, we propose spare assignement algorithm. Based on an existing range-cheking-first algorithm (RCFA), we propose assign-all-row-RCFA (A-RCFA) which assign unused spare rows to faulty ones, in order to suppress the degradation of repair rate due to compressed fail location information output from the encoder-based comparator. Then, considering that an SoC has many SRAM modules, we propose a heuristic algorithm based on iterative improvement algorithm (IIA), which determines whether each SRAM should have a spare row or not, in order to minimize area per a good die. Experimental results on practical scale benchmark SoCs with more than 1,000 SRAM modules indicate that encoder-based comparators reduce hardware overhead by about 50% compared to traditional ones, and that combining the IIA-based algorithm for determining redundancy architecture with the encoder-based comparator effectively reduces the area per good die.},
keywords={},
doi={10.1587/transfun.E93.A.2463},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Reduction of Area per Good Die for SoC Memory Built-In Self-Test
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2463
EP - 2471
AU - Masayuki ARAI
AU - Tatsuro ENDO
AU - Kazuhiko IWASAKI
AU - Michinobu NAKAO
AU - Iwao SUZUKI
PY - 2010
DO - 10.1587/transfun.E93.A.2463
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - To reduce the manufacturing cost of SoCs with many embedded SRAMs, we propose a scheme to reduce the area per good die for the SoC memory built-in self-test (MBIST). We first propose BIST hardware overhead reduction by application of an encoder-based comparator. For the repair of a faulty SRAM module with 2-D redundancy, we propose spare assignement algorithm. Based on an existing range-cheking-first algorithm (RCFA), we propose assign-all-row-RCFA (A-RCFA) which assign unused spare rows to faulty ones, in order to suppress the degradation of repair rate due to compressed fail location information output from the encoder-based comparator. Then, considering that an SoC has many SRAM modules, we propose a heuristic algorithm based on iterative improvement algorithm (IIA), which determines whether each SRAM should have a spare row or not, in order to minimize area per a good die. Experimental results on practical scale benchmark SoCs with more than 1,000 SRAM modules indicate that encoder-based comparators reduce hardware overhead by about 50% compared to traditional ones, and that combining the IIA-based algorithm for determining redundancy architecture with the encoder-based comparator effectively reduces the area per good die.
ER -
English
