IEICE TRANSACTIONS on Fundamentals
A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm
Summary :
This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27×0.36mm2, is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25°C is 3µs. The average reduction energy is at least 42% from 0°C to 100°C.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.12 pp.2592-2599
- Publication Date
- 2015/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.2592
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Circuit Design
Authors
Keisuke OKUNO
Kobe University
Shintaro IZUMI
Kobe University
Kana MASAKI
Kobe University
Hiroshi KAWAGUCHI
Kobe University
Masahiko YOSHIMOTO
Kobe University
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Keisuke OKUNO, Shintaro IZUMI, Kana MASAKI, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, "A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 12, pp. 2592-2599, December 2015, doi: 10.1587/transfun.E98.A.2592.
Abstract: This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27×0.36mm2, is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25°C is 3µs. The average reduction energy is at least 42% from 0°C to 100°C.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.2592/_p
Copy
@ARTICLE{e98-a_12_2592,
author={Keisuke OKUNO, Shintaro IZUMI, Kana MASAKI, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm},
year={2015},
volume={E98-A},
number={12},
pages={2592-2599},
abstract={This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27×0.36mm2, is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25°C is 3µs. The average reduction energy is at least 42% from 0°C to 100°C.},
keywords={},
doi={10.1587/transfun.E98.A.2592},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2592
EP - 2599
AU - Keisuke OKUNO
AU - Shintaro IZUMI
AU - Kana MASAKI
AU - Hiroshi KAWAGUCHI
AU - Masahiko YOSHIMOTO
PY - 2015
DO - 10.1587/transfun.E98.A.2592
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2015
AB - This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27×0.36mm2, is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25°C is 3µs. The average reduction energy is at least 42% from 0°C to 100°C.
ER -
English
