IEICE TRANSACTIONS on Information
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths
Summary :
This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.8 pp.1940-1947
- Publication Date
- 2005/08/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.8.1940
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
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Zhiqiang YOU, Ken'ichi YAMAGUCHI, Michiko INOUE, Jacob SAVIR, Hideo FUJIWARA, "Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 8, pp. 1940-1947, August 2005, doi: 10.1093/ietisy/e88-d.8.1940.
Abstract: This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.8.1940/_p
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@ARTICLE{e88-d_8_1940,
author={Zhiqiang YOU, Ken'ichi YAMAGUCHI, Michiko INOUE, Jacob SAVIR, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths},
year={2005},
volume={E88-D},
number={8},
pages={1940-1947},
abstract={This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches.},
keywords={},
doi={10.1093/ietisy/e88-d.8.1940},
ISSN={},
month={August},}
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TY - JOUR
TI - Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths
T2 - IEICE TRANSACTIONS on Information
SP - 1940
EP - 1947
AU - Zhiqiang YOU
AU - Ken'ichi YAMAGUCHI
AU - Michiko INOUE
AU - Jacob SAVIR
AU - Hideo FUJIWARA
PY - 2005
DO - 10.1093/ietisy/e88-d.8.1940
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2005
AB - This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve low hardware overheads. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm the good performance and practicality of our new approaches.
ER -
English
