IEICE TRANSACTIONS on Information
Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions
Summary :
It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1
- Publication
- IEICE TRANSACTIONS on Information Vol.E82-D No.9 pp.1278-1286
- Publication Date
- 1999/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Fault Tolerant Computing
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Takashi HIRAYAMA, Goro KODA, Yasuaki NISHITANI, Kensuke SHIMIZU, "Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 9, pp. 1278-1286, September 1999, doi: .
Abstract: It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_9_1278/_p
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@ARTICLE{e82-d_9_1278,
author={Takashi HIRAYAMA, Goro KODA, Yasuaki NISHITANI, Kensuke SHIMIZU, },
journal={IEICE TRANSACTIONS on Information},
title={Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions},
year={1999},
volume={E82-D},
number={9},
pages={1278-1286},
abstract={It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions
T2 - IEICE TRANSACTIONS on Information
SP - 1278
EP - 1286
AU - Takashi HIRAYAMA
AU - Goro KODA
AU - Yasuaki NISHITANI
AU - Kensuke SHIMIZU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1999
AB - It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1
ER -
English
