IEICE TRANSACTIONS on Information
Analysis of IDDQ Occurrence in Testing
Summary :
This work presents an analysis of IDDQ dependency on the primary current that flows through the bridging fault and driven gates current. A maximum primary current depends only on the test vectors which minimize channel resistances of transistors. The driven gates current generates when intermediate voltage occurs on the faulty node with creation current path between VDD and GND through the driven gates, and its value depends on circuit parameters such as transistor sizes and fan-in number of driven gates.
- Publication
- IEICE TRANSACTIONS on Information Vol.E84-D No.4 pp.534-536
- Publication Date
- 2001/04/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Computer System Element
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Keyword
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Arabi KESHK, Yukiya MIURA, Kozo KINOSHITA, "Analysis of IDDQ Occurrence in Testing" in IEICE TRANSACTIONS on Information,
vol. E84-D, no. 4, pp. 534-536, April 2001, doi: .
Abstract: This work presents an analysis of IDDQ dependency on the primary current that flows through the bridging fault and driven gates current. A maximum primary current depends only on the test vectors which minimize channel resistances of transistors. The driven gates current generates when intermediate voltage occurs on the faulty node with creation current path between VDD and GND through the driven gates, and its value depends on circuit parameters such as transistor sizes and fan-in number of driven gates.
URL: https://global.ieice.org/en_transactions/information/10.1587/e84-d_4_534/_p
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@ARTICLE{e84-d_4_534,
author={Arabi KESHK, Yukiya MIURA, Kozo KINOSHITA, },
journal={IEICE TRANSACTIONS on Information},
title={Analysis of IDDQ Occurrence in Testing},
year={2001},
volume={E84-D},
number={4},
pages={534-536},
abstract={This work presents an analysis of IDDQ dependency on the primary current that flows through the bridging fault and driven gates current. A maximum primary current depends only on the test vectors which minimize channel resistances of transistors. The driven gates current generates when intermediate voltage occurs on the faulty node with creation current path between VDD and GND through the driven gates, and its value depends on circuit parameters such as transistor sizes and fan-in number of driven gates.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Analysis of IDDQ Occurrence in Testing
T2 - IEICE TRANSACTIONS on Information
SP - 534
EP - 536
AU - Arabi KESHK
AU - Yukiya MIURA
AU - Kozo KINOSHITA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E84-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2001
AB - This work presents an analysis of IDDQ dependency on the primary current that flows through the bridging fault and driven gates current. A maximum primary current depends only on the test vectors which minimize channel resistances of transistors. The driven gates current generates when intermediate voltage occurs on the faulty node with creation current path between VDD and GND through the driven gates, and its value depends on circuit parameters such as transistor sizes and fan-in number of driven gates.
ER -
English
