IEICE TRANSACTIONS on Information
Generation of Test Sequences with Low Power Dissipation for Sequential Circuits
Summary :
When LSIs that are designed and manufactured for low power dissipation are tested, test vectors that make the power dissipation low should be applied. If test vectors that cause high power dissipation are applied, incorrect test results are obtained or circuits under test are permanently damaged. In this paper, we propose a method to generate test sequences with low power dissipation for sequential circuits. We assume test sequences generated by an ATPG tool are given, and modify them while keeping the original stuck-at fault coverages. The test sequence is modified by inverting the values of primary inputs of every test vector one by one. In order to keep the original fault coverage, fault simulation is conducted whenever one value of primary inputs is inverted. We introduce heuristics that perform fault simulation for a subset of faults during the modification of test vectors. This helps reduce the power dissipation of the modified test sequence. If the fault coverage by the modified test sequence is lower than that by the original test sequence, we generate a new short test sequence and add it to the modified test sequence.
- Publication
- IEICE TRANSACTIONS on Information Vol.E87-D No.3 pp.530-536
- Publication Date
- 2004/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Test and Verification of VLSI)
- Category
- Test Generation and Compaction
Authors
Keyword
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Yoshinobu HIGAMI, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, "Generation of Test Sequences with Low Power Dissipation for Sequential Circuits" in IEICE TRANSACTIONS on Information,
vol. E87-D, no. 3, pp. 530-536, March 2004, doi: .
Abstract: When LSIs that are designed and manufactured for low power dissipation are tested, test vectors that make the power dissipation low should be applied. If test vectors that cause high power dissipation are applied, incorrect test results are obtained or circuits under test are permanently damaged. In this paper, we propose a method to generate test sequences with low power dissipation for sequential circuits. We assume test sequences generated by an ATPG tool are given, and modify them while keeping the original stuck-at fault coverages. The test sequence is modified by inverting the values of primary inputs of every test vector one by one. In order to keep the original fault coverage, fault simulation is conducted whenever one value of primary inputs is inverted. We introduce heuristics that perform fault simulation for a subset of faults during the modification of test vectors. This helps reduce the power dissipation of the modified test sequence. If the fault coverage by the modified test sequence is lower than that by the original test sequence, we generate a new short test sequence and add it to the modified test sequence.
URL: https://global.ieice.org/en_transactions/information/10.1587/e87-d_3_530/_p
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@ARTICLE{e87-d_3_530,
author={Yoshinobu HIGAMI, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, },
journal={IEICE TRANSACTIONS on Information},
title={Generation of Test Sequences with Low Power Dissipation for Sequential Circuits},
year={2004},
volume={E87-D},
number={3},
pages={530-536},
abstract={When LSIs that are designed and manufactured for low power dissipation are tested, test vectors that make the power dissipation low should be applied. If test vectors that cause high power dissipation are applied, incorrect test results are obtained or circuits under test are permanently damaged. In this paper, we propose a method to generate test sequences with low power dissipation for sequential circuits. We assume test sequences generated by an ATPG tool are given, and modify them while keeping the original stuck-at fault coverages. The test sequence is modified by inverting the values of primary inputs of every test vector one by one. In order to keep the original fault coverage, fault simulation is conducted whenever one value of primary inputs is inverted. We introduce heuristics that perform fault simulation for a subset of faults during the modification of test vectors. This helps reduce the power dissipation of the modified test sequence. If the fault coverage by the modified test sequence is lower than that by the original test sequence, we generate a new short test sequence and add it to the modified test sequence.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Generation of Test Sequences with Low Power Dissipation for Sequential Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 530
EP - 536
AU - Yoshinobu HIGAMI
AU - Shin-ya KOBAYASHI
AU - Yuzo TAKAMATSU
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E87-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2004
AB - When LSIs that are designed and manufactured for low power dissipation are tested, test vectors that make the power dissipation low should be applied. If test vectors that cause high power dissipation are applied, incorrect test results are obtained or circuits under test are permanently damaged. In this paper, we propose a method to generate test sequences with low power dissipation for sequential circuits. We assume test sequences generated by an ATPG tool are given, and modify them while keeping the original stuck-at fault coverages. The test sequence is modified by inverting the values of primary inputs of every test vector one by one. In order to keep the original fault coverage, fault simulation is conducted whenever one value of primary inputs is inverted. We introduce heuristics that perform fault simulation for a subset of faults during the modification of test vectors. This helps reduce the power dissipation of the modified test sequence. If the fault coverage by the modified test sequence is lower than that by the original test sequence, we generate a new short test sequence and add it to the modified test sequence.
ER -
English
